AN 961: IO Module Design Example for OPC UA: for Intel® MAX® 10 Devices

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ID 691266
Date 10/30/2021
Public
Document Table of Contents
Document Table of Contents x
About the IO Module Design Example for Intel® MAX® 10 Devices for OPC UA Getting Started with the IO Module Design Example for OPC UA Functional Description Known Issues with the IO Module Design Example Document Revision History for AN 961: IO Module Design Example for Intel® MAX® 10 Devices for OPC UA
About the IO Module Design Example for Intel® MAX® 10 Devices for OPC UA x
Features OPC UA Nodes Performance and Resource Utilization for the IO Module Design Example for OPC UA
Getting Started with the IO Module Design Example for OPC UA x
Hardware and Software Requirements for the IO Module Design Example for OPC UA Downloading the IO Module Design Example for OPC UA Installing FreeRTOS and LwIP Templates on Nios Eclipse IDE Generating an open62541 OPC UA Amalgamation (optional) Preparing the IO Module Project for Build Adding IO Module Software Running the IO Module Design Example Achieving Timing Closure on a Design Example
About the IO Module Design Example for Intel® MAX® 10 Devices for OPC UA
Getting Started with the IO Module Design Example for OPC UA
Functional Description
Known Issues with the IO Module Design Example
Document Revision History for AN 961: IO Module Design Example for Intel® MAX® 10 Devices for OPC UA

About the IO Module Design Example for Intel® MAX® 10 Devices for OPC UA

The design demonstrates the usability of a low-power FPGA as an IO module, providing compute at the edge. The design shows how FPGAs implement different hardware modules such as triple-speed Ethernet controllers, digital inputs, digital outputs, and Nios II soft processors.

The design is a low-cost IO module that can be part of an industrial network using OPC unified architecture (UA) communication over Ethernet. The design shows you can add small devices such as Intel® MAX® 10 FPGAs to an industrial network to perform basic but necessary tasks like IO supervision and monitoring. For more information on OPC UA, refer to the OPC Foundation website

The design provides an interface to the IO using an OPC UA client and server model and OPC UA PubSub. The design implements all this hardware in the FPGA allowing rapid prototyping and application of changes in the field.

The design’s open-source software with FreeRTOS manages the running and scheduling, making the application scalable, reliable, and deterministic.
Figure 1. Basic Setup
Figure 2. Block diagramThe hardware and software allow you to implement small devices that perform a specific task within an Industry 4.0 network. Industry 4.0 allows workload consolidation at the edge and real-time connectivity between the industrial.

The design:

  • Demonstrates industrial networking standards OPC UA Client-Server, OPC UA PubSub, and IO on a real LAN with many affordable and application-specific devices.
  • Provides the TCP/IP services required to connect the device to a LAN by a lightweight version of TCP/IP stack known as lightweight IP (lwIP), compatible with FreeRTOS.
  • Implements the high-level user application, either OPC UA Client-Server or OPC UA PubSub, using open62541 in amalgamation mode.
  • Targets the Intel MAX 10 development board.
  • Is compatible with FreeRTOS and lwIP. For more information on FreeRTOS, refer to the FreeRTOS website.

Features

On the Intel MAX 10 Development Board, the design offers:

  • An Ethernet interface for onboard IO with an OPC UA server.
  • Support for both Ethernet ports.
  • Up to 1000 Mbps transfer rate.
  • 11 ms minimum OPC UA publishing cycle time (four static and four dynamic datasets).
  • ADC: 64 sequencing channels with sample rate of 1 MHz with internal reference 2.5 V.
  • Onboard LEDs, push buttons, and on-chip temperature sensing diode.
  • Total thermal power dissipation of 754.52 mW.

OPC UA Nodes

OPC UA includes several nodes that correspond to a specific IO on the Intel MAX 10 development board. Two additional nodes measure the delta time between IO data updates and the time difference between each publishing cycle (cycle time). Each of these nodes has a corresponding update function that you can call every publishing cycle either on the read or write to the OPC UA dataset.

Table 1.  OPC UA nodes

The configured nodes represent the selected IO and read or write from the corresponding IO pins. Each node is configured with a name, ID, type, access level, and parent node. You can use each of these as filters to select which nodes on the network to input. The design ignores anything not matching.

Name Node ID Type Access Update Function
LED value LED-value UA_Int32 Write setLED()
Push button array Pb-matrix UA_Double[4] Read getPB()
Onboard temp Onboard-temp UA_Int32 Read getTemp()
Current time Current-time-data-source UA_DateTime Read updateCurrentTime()
Publishing cycle time Cycle-time UA_Int32 Read readCycleTime()
Related Information
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