Functional Description
The IO Module Design Example for OPC UA targets the Intel MAX 10 development board as the IO module device. This device allows development using on-chip peripherals, CPU, and triple-speed Ethernet controllers.
The design is based on an Intel Ethernet design from the Intel Simple Socket Server design example. It has a top-level subsystem and two subsystems: one peripheral subsystem, and an Ethernet subsystem. This system design uses an Avalon Memory-Mapped interface, a DDR3 RAM, and Nios-II soft processor IP to provide an interface between peripherals, and a triple-speed Ethernet controller. The peripherals include an onboard GPIO with LEDs and pushbuttons, and on-chip IP including timer, ADC, and temperature sensing diode. The design can run the OPC UA PubSub or Client-Server software. The triple-speed Ethernet IP uses the RGMII standard to run at 1000 Mb/s transfer speeds. A clock control subsystem, which determines the suitable clock based on the Ethernet connection type, selects varying clock times. The ADC uses 64 sequencing channels with a sample rate of 1 MHz set by default and an internal reference of 2.5 V.
Figure 17. IO Module Design Example Hardware Block Diagram
Clocks
The main system clock source is 50 MHz and is driven by the Intel MAX 10 50 MHz clock pin. This system clock drives the two PLLs: altpll_0 for TSE RGMII timing and altpll_100 for the 100 MHz clock supplied to the IO and Nios II processor. An additional 100 MHz clock pin drives the external DDR3 RAM Interface to meet timing constraints.
Figure 18. System clock and PLL dependencies
ADC Sampling
The IO module has ADC sampling using an on-chip temperature sensing diode. The Nios II processor reads these analog inputs interfacing them with an ADC IP that is programmed into the FPGA fabric. The modular ADC IP acts as a soft controller for the two ADC hard IP blocks on the FPGA. The first ADC has 10 channels: 9 input channels and a dedicated channel for the temperature sensing diode. The ADC sample rate automatically changes from 1 megasamples/s on normal channel input mode to 50 kilosamples/s on temperature sensing diode channel mode, which samples at a 64-sample running average method.
The ADC sequencer specifies which channel is sampled at which time and a certain number of samples. The sequencer is built into the modular ADC IP. The handling is based on channel selection, sample rate, ADC clock, and the reference voltage.
Software
The design software runs on the Nios II processor and is primarily programmed in embedded C using the Nios-II Eclipse IDE. The project includes a .bsp file, which contains all the FPGA driver files, FreeRTOS source files, and LwIP source files. The software includes the main thread and two sub-threads: xEthernetRun for network initialization and opcua_pub for the OPC UA publishing.
Figure 19. OPC UA thread flowchart for a PubSub Publisher
To read to or write from GPIOs such as LEDs and push buttons, the design calls a driver command with the corresponding pin. The ADC requires a setup command to begin the sequencer and then you can read as IO. The design converts the input for the temperature sensing diode into a Celsius value using a lookup table provided in the temperature sensing diode design example.