DisplayPort Stratix® 10 FPGA IP Design Example User Guide

ID 683887
Date 4/10/2024
Public
Document Table of Contents

2.2.1. Stratix® 10 DisplayPort SST TX-only Design Features

The TX-only design example demonstrates the transmission of a single video stream from DisplayPort Sink to DisplayPort Source.
Figure 7.  Stratix® 10 DisplayPort SST TX-only
  • To generate this TX-only variant, turn on the DisplayPort source TX SUPPORT DP parameter and turn off the DisplayPort sink RX SUPPORT DP parameter.
  • This variant uses the standard VSYNC/HSYNC/DE video interface, while the DisplayPort source’s TX SUPPORT IM ENABLE parameter is turned off.
  • For video source, this variant integrates Test Pattern Generator II and Clocked Video Output II to display 1080p60 color bar image.
  • The IOPLL drives the video clock at a 300 MHz to CVO II and 37.125 MHz (4 pixel per clock) to TPG II.
  • Before programming SOF file to the development kit, set OUT4 and OUT5 frequency of Si5341A (U7) to 100 MHz in the Clock Control GUI for the tx_vid_pll reference clock.