4G Turbo-V Intel® FPGA IP User Guide

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ID 683882
Date 11/18/2020
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Document Table of Contents
Document Table of Contents x
1. About the 4G Turbo-V Intel® FPGA IP 2. Designing with the 4G Turbo-V Intel® FPGA IP 3. 4G Turbo-V Intel® FPGA IP Functional Description 4. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide
1. About the 4G Turbo-V Intel® FPGA IP x
1.1. 4G Turbo-V Intel® FPGA IP Features 1.2. 4G Turbo-V Intel® FPGA IP Device Family Support 1.3. Release Information for the 4G Turbo-V Intel® FPGA IP 1.4. 4G Turbo-V Performance and Resource Utilization
2. Designing with the 4G Turbo-V Intel® FPGA IP x
2.1. 4G Turbo-V IP Directory Structure 2.2. Generating a 4G Turbo-V IP 2.3. Simulating a 4G Turbo-V IP
3. 4G Turbo-V Intel® FPGA IP Functional Description x
3.1. 4G Turbo-V Architecture 3.2. 4G Turbo-V Signals and Interfaces 3.3. 4G Turbo-V Timing Diagrams 3.4. 4G Turbo-V Latency and Throughput
3.2. 4G Turbo-V Signals and Interfaces x
3.2.1. Avalon Streaming Interfaces in DSP Intel FPGA IP
1. About the 4G Turbo-V Intel® FPGA IP
2. Designing with the 4G Turbo-V Intel® FPGA IP
3. 4G Turbo-V Intel® FPGA IP Functional Description
4. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide

2.2. Generating a 4G Turbo-V IP

You can generate a downlink or uplink accelerator. For the uplink accelerator, replace dl with ul in directory or file names.
  1. Open the Intel Quartus Prime Pro software.
  2. Select File > New Project Wizard.
  3. Click Next.
  4. Enter Project name dl_fec_wrapper_top and enter the project location.
  5. Select Arria 10 device.
  6. Click Finish.
  7. Open the dl_fec_wrapper_top.qpf file available at project directory
    The project wizard appears.
  8. On the Platform Designer tab:
    1. Create the dl_fec_wrapper_top.ip file using hardware tcl file.
    2. Click Generate HDL to generate the design files.
  9. On the Generate tab, click Generate Test bench system.
  10. Click Add All to add the synthesis files to the project.
    The files are in src\ip\dl_fec_wrapper_top\dl_fec_wrapper_10\synth.
  11. Set dl_fec_wrapper_top.v file as top level entity.
  12. Click Start Compilation to compile this project.
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