4G Turbo-V Intel® FPGA IP User Guide

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ID 683882
Date 11/18/2020
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Document Table of Contents
Document Table of Contents x
1. About the 4G Turbo-V Intel® FPGA IP 2. Designing with the 4G Turbo-V Intel® FPGA IP 3. 4G Turbo-V Intel® FPGA IP Functional Description 4. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide
1. About the 4G Turbo-V Intel® FPGA IP x
1.1. 4G Turbo-V Intel® FPGA IP Features 1.2. 4G Turbo-V Intel® FPGA IP Device Family Support 1.3. Release Information for the 4G Turbo-V Intel® FPGA IP 1.4. 4G Turbo-V Performance and Resource Utilization
2. Designing with the 4G Turbo-V Intel® FPGA IP x
2.1. 4G Turbo-V IP Directory Structure 2.2. Generating a 4G Turbo-V IP 2.3. Simulating a 4G Turbo-V IP
3. 4G Turbo-V Intel® FPGA IP Functional Description x
3.1. 4G Turbo-V Architecture 3.2. 4G Turbo-V Signals and Interfaces 3.3. 4G Turbo-V Timing Diagrams 3.4. 4G Turbo-V Latency and Throughput
3.2. 4G Turbo-V Signals and Interfaces x
3.2.1. Avalon Streaming Interfaces in DSP Intel FPGA IP
1. About the 4G Turbo-V Intel® FPGA IP
2. Designing with the 4G Turbo-V Intel® FPGA IP
3. 4G Turbo-V Intel® FPGA IP Functional Description
4. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide

3.1. 4G Turbo-V Architecture

The 4G Turbo-V Intel® FPGA IP comprises a downlink accelerator and an uplink accelerator.

4G Downlink Accelerator

Figure 3. 4G Downlink AcceleratorThe 4G Turbo downlink accelerator consists of a code block CRC attachment block and a Turbo encoder (Intel Turbo FPGA IP) and rate matcher. The input data is 8-bit wide and the output data is 24-bit wide. The rate matcher consists of three subblock interleavers, a bit selector, and a bit collector.

The 4G downlink accelerator implements a code block CRC attachment with 8-bit parallel CRC computation algorithm. The input to the CRC attachment block is 8-bit wide. In the normal mode, the number of inputs to the CRC block is k-24, where k is the block size based on the size index. The additional CRC sequence of 24 bits is attached to the incoming code block of data in the CRC attachment block and then passes to the Turbo encoder. In the CRC bypass mode, the number of inputs is k size of 8-bit wide passed to the Turbo encoder block.

The Turbo encoder uses a parallel concatenated convolutional code. A convolutional encoder encodes an information sequence and another convolutional encoder encodes an interleaved version of the information sequence. The Turbo encoder has two 8-state constituent convolutional encoders and one Turbo code internal interleaver. For more information about the Turbo encoder, refer to the Turbo IP Core User Guide.

The rate matcher matches the number of bits in transport block to the number of bits that the IP transmits in that allocation. The input and output of the rate matcher is 24 bits. The IP defines the rate matching for Turbo coded transport channels for each code block. The rate matcher comprises: subblock interleaver, bit collector and bit selector.

The downlink accelerator sets up the subblock interleaver for each output stream from Turbo coding. The streams include a message bit stream, 1st parity bit stream and 2nd parity bit stream.

The input and output of the subblock interleaver is 24 bits wide.

The bit collector combines the streams that come from the subblock interleaver. This block contains buffers that store:

  • Messages and filler enabling bits from the subblock interleaver.
  • The subblock interleaver parity bits and their respective filler bits.
Figure 4. Bit Collector

4G Channel Uplink Accelerator

Figure 5. 4G Channel Uplink AcceleratorThe 4G Turbo uplink accelerator consists of an subblock deinterleaver and a turbo decoder (Intel Turbo FPGA IP).

The deinterleaver consists of three blocks in which the first two blocks are symmetrical and the third block is different.

The latency of the ready signal is 0.

Figure 6. Deinterleaver

If you turn on the bypass mode for the subblock deinterleaver, the IP reads the data as it writes the data in the memory blocks in the successive locations. The IP reads the data as and when it writes the data without any interleaving. The number of input data into the subblock deinterleaver is K_π in the bypass mode and the output data length is k size (k is the code block size based on the cb_size_index value).

The latency of the output data of the subblock deinterleaver depends on the input block size K_π. The IP reads the data only after you write the K_π code block size of input data. Hence the latency of the output also includes the write time. The latency in the subblock interleaver output data is K_π+17.

The Turbo decoder calculates the most likely transmitted sequence, based on the samples that it receives. For a detailed explanation, refer to the Turbo Core IP User Guide. Decoding of error correcting codes is a comparison of the probabilities for different convolutional codes. The Turbo decoder consists of two single soft-in soft-out (SISO) decoders, which work iteratively. The output of the first (upper decoder) feeds into the second to form a Turbo decoding iteration. Interleaver and deinterleaver blocks reorder data in this process.

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