4G Turbo-V Intel® FPGA IP User Guide

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ID 683882
Date 11/18/2020
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Document Table of Contents
Document Table of Contents x
1. About the 4G Turbo-V Intel® FPGA IP 2. Designing with the 4G Turbo-V Intel® FPGA IP 3. 4G Turbo-V Intel® FPGA IP Functional Description 4. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide
1. About the 4G Turbo-V Intel® FPGA IP x
1.1. 4G Turbo-V Intel® FPGA IP Features 1.2. 4G Turbo-V Intel® FPGA IP Device Family Support 1.3. Release Information for the 4G Turbo-V Intel® FPGA IP 1.4. 4G Turbo-V Performance and Resource Utilization
2. Designing with the 4G Turbo-V Intel® FPGA IP x
2.1. 4G Turbo-V IP Directory Structure 2.2. Generating a 4G Turbo-V IP 2.3. Simulating a 4G Turbo-V IP
3. 4G Turbo-V Intel® FPGA IP Functional Description x
3.1. 4G Turbo-V Architecture 3.2. 4G Turbo-V Signals and Interfaces 3.3. 4G Turbo-V Timing Diagrams 3.4. 4G Turbo-V Latency and Throughput
3.2. 4G Turbo-V Signals and Interfaces x
3.2.1. Avalon Streaming Interfaces in DSP Intel FPGA IP
1. About the 4G Turbo-V Intel® FPGA IP
2. Designing with the 4G Turbo-V Intel® FPGA IP
3. 4G Turbo-V Intel® FPGA IP Functional Description
4. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide

1.4. 4G Turbo-V Performance and Resource Utilization

Intel generated the resource utilization and performance by compiling the designs with Intel Quartus Prime software v19.1. Only use these approximate results for early estimation of FPGA resources (e.g. adaptive logic modules (ALMs)) that a project requires. The target frequency is 300 MHz.
Table 3.  Downlink Accelerator Resource Utilization and Maximum Frequency for Intel Arria 10 Devices
Module fMAX (MHz) ALMs ALUTs Registers Memory (Bits) RAM Blocks (M20K) DSP Blocks
Downlink accelerator 325.63 9,373 13,485 14,095 297,472 68 8
CRC attachment 325.63 39 68 114 0 0 0
Turbo encoder 325.63 1,664 2,282 1154 16,384 16 0
Rate matcher 325.63 7,389 10,747 12,289 274,432 47 8
Subblock interleaver 325.63 2,779 3,753 5,559 52,416 27 0
Bit collector 325.63 825 1,393 2,611 118,464 13 4
Bit selector and pruner 325.63 3,784 5,601 4,119 103,552 7 4
Table 4.  Uplink Accelerator Resource Utilization and Maximum Frequency for Intel Arria 10 Devices
Module fMAX (MHz) ALMs Registers Memory (Bits) RAM Blocks (M20K) DSP Blocks
Uplink accelerator 314.76 29480 30,280 868,608 71 0
Subblock deinterleaver 314.76 253 830 402,304 27 0
Turbo decoder 314.76 29,044 29,242 466,304 44 0
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