4G Turbo-V Intel® FPGA IP User Guide

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ID 683882
Date 11/18/2020
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Document Table of Contents
Document Table of Contents x
1. About the 4G Turbo-V Intel® FPGA IP 2. Designing with the 4G Turbo-V Intel® FPGA IP 3. 4G Turbo-V Intel® FPGA IP Functional Description 4. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide
1. About the 4G Turbo-V Intel® FPGA IP x
1.1. 4G Turbo-V Intel® FPGA IP Features 1.2. 4G Turbo-V Intel® FPGA IP Device Family Support 1.3. Release Information for the 4G Turbo-V Intel® FPGA IP 1.4. 4G Turbo-V Performance and Resource Utilization
2. Designing with the 4G Turbo-V Intel® FPGA IP x
2.1. 4G Turbo-V IP Directory Structure 2.2. Generating a 4G Turbo-V IP 2.3. Simulating a 4G Turbo-V IP
3. 4G Turbo-V Intel® FPGA IP Functional Description x
3.1. 4G Turbo-V Architecture 3.2. 4G Turbo-V Signals and Interfaces 3.3. 4G Turbo-V Timing Diagrams 3.4. 4G Turbo-V Latency and Throughput
3.2. 4G Turbo-V Signals and Interfaces x
3.2.1. Avalon Streaming Interfaces in DSP Intel FPGA IP
1. About the 4G Turbo-V Intel® FPGA IP
2. Designing with the 4G Turbo-V Intel® FPGA IP
3. 4G Turbo-V Intel® FPGA IP Functional Description
4. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide

3.4. 4G Turbo-V Latency and Throughput

The latency is measured between input first packet SOP to output first packet SOP. The processing time is measured between input first packet SOP to output last packet EOP.

Downlink accelerator

The throughput is the rate at which the IP can pump the input into the downlink accelerator as it is ready.

Table 7.  Downlink Accelerator Latency, Processing Time, and ThroughputWith the maximum K size of 6,144 and E size of 11,522. Processing time measured for 13 code blocks. Clock speed is 300 MHz.
K E Latency

Processing time

Input

Throughput

    (cycles) (us) (cycles) (us) (%)
6,144 11,552 3,550 11.8 14,439 48.13 95
Figure 15. Latency and Processing Time Calculation

The figure shows the procedure to calculate latency, processing time, and throughput.

Figure 16. K Size versus Latency
Figure 17. K Size versus Latencyk=40 to 1408

Uplink Accelerator

Table 8.  Uplink Accelerator Latency and Processing TimeWith max iteration number = 6. Clock speed is 300 MHz.
K E Latency Processing time
    (cycles) (us) (cycles) (us)
86 40 316 1.05 318 1.06
34,560 720 2,106 7.02 2,150 7.16
34,560 1,408 3,802 12.67 3,889 12.96
34,560 1,824 4,822 16.07 4,935 16.45
28,788 2,816 7,226 24.08 7,401 24.67
23,742 3,520 8,946 29.82 9,165 30.55
34,560 4,032 10,194 33.98 10,445 34.81
26,794 4,608 11,594 38.64 11,881 39.60
6,480 5,504 13,786 45.95 14,129 47.09
12,248 6,144 15,338 51.12 15,721 52.40
Table 9.  Uplink Accelerator Latency and Processing TimeWith max iteration number = 8
K E Latency Processing time
    (cycles) (us) (cycles) (us)
86 40 366 1.22 368 1.22
34,560 720 2,290 7.63 2,334 7.78
34,560 1,408 4,072 13.57 4,159 13.86
34,560 1,824 5,144 17.14 5,257 17.52
28,788 2,816 7,672 25.57 7,847 26.15
23,742 3,520 9,480 31.6 9,699 32.33
34,560 4,032 10,792 35.97 11,043 36.81
26,794 4,608 12,264 40.88 12,551 41.83
6,480 5,504 14,568 48.56 14,911 49.70
12,248 6,144 16,200 54 16,583 55.27
Figure 18. K Size vs Latency For max_iter=6
Figure 19. K Size vs Processing Time For max_iter=6
Figure 20. K Size vs Latency For max_iter=8
Figure 21. K Size vs Processing Time For max_iter=8

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