4G Turbo-V Intel® FPGA IP User Guide

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ID 683882
Date 11/18/2020
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Document Table of Contents
Document Table of Contents x
1. About the 4G Turbo-V Intel® FPGA IP 2. Designing with the 4G Turbo-V Intel® FPGA IP 3. 4G Turbo-V Intel® FPGA IP Functional Description 4. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide
1. About the 4G Turbo-V Intel® FPGA IP x
1.1. 4G Turbo-V Intel® FPGA IP Features 1.2. 4G Turbo-V Intel® FPGA IP Device Family Support 1.3. Release Information for the 4G Turbo-V Intel® FPGA IP 1.4. 4G Turbo-V Performance and Resource Utilization
2. Designing with the 4G Turbo-V Intel® FPGA IP x
2.1. 4G Turbo-V IP Directory Structure 2.2. Generating a 4G Turbo-V IP 2.3. Simulating a 4G Turbo-V IP
3. 4G Turbo-V Intel® FPGA IP Functional Description x
3.1. 4G Turbo-V Architecture 3.2. 4G Turbo-V Signals and Interfaces 3.3. 4G Turbo-V Timing Diagrams 3.4. 4G Turbo-V Latency and Throughput
3.2. 4G Turbo-V Signals and Interfaces x
3.2.1. Avalon Streaming Interfaces in DSP Intel FPGA IP
1. About the 4G Turbo-V Intel® FPGA IP
2. Designing with the 4G Turbo-V Intel® FPGA IP
3. 4G Turbo-V Intel® FPGA IP Functional Description
4. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide

3.3. 4G Turbo-V Timing Diagrams

Downlink Accelerator

Figure 9. Timing Diagram for Write Logic with Codeblock 40The IP:
  • Places null 20 bits in column 0 to 19 and writes the data bits from column 20.
  • Writes all 44 bits to memory in 6 clock cycles.
  • Writes trellis termination bits into column 28 to 31.
  • Increments write address for each row.
  • Generates write enable signal for 8 individual RAM at a time.
The IP does not write filler bits into RAM. Instead, the IP leaves the place holder for filter bits in the RAM and inserts the NULL bits into the output during the read process. The first write starts from column 20.
Figure 10. Timing Diagram for Read Logic with Codeblock 40For each read, you see 8 bits in one clock cycle but only two bits are valid. The IP writes these two bits into the shift register. When the IP forms 8 bits it sends them to the output interface.
Figure 11. Timing Diagram for Write Logic with Codeblock 6144The filler bits are from column 0 to 27 and the data bits are from column 28. The IP:
  • Writes all 6,148 bits to memory in 769 clock cycles.
  • Writes trellis termination bits into column 28 to 31.
  • Increments write address for each row.
  • Generates write enable signal generated for 8 individual RAM at a time.
The IP does not write filler bits into RAM. Instead the IP leaves the place holder for filter bits over in the RAM and inserts the NULL bits into output during the read process. The first write starts from column 28.
Figure 12. Timing Diagram for Read Logic with Codeblock 6144On the read side, each read gives 8 bits. While reading the 193rd row, the IP read 8 bits, but only one bit is valid. The IP forms eight bits with shift registers and sends them out by reading from the next column.

Uplink Accelerator

Figure 13. Input Timing Diagram
Figure 14. Output Timing Diagram
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