4G Turbo-V Intel® FPGA IP User Guide

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ID 683882
Date 11/18/2020
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Document Table of Contents
Document Table of Contents x
1. About the 4G Turbo-V Intel® FPGA IP 2. Designing with the 4G Turbo-V Intel® FPGA IP 3. 4G Turbo-V Intel® FPGA IP Functional Description 4. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide
1. About the 4G Turbo-V Intel® FPGA IP x
1.1. 4G Turbo-V Intel® FPGA IP Features 1.2. 4G Turbo-V Intel® FPGA IP Device Family Support 1.3. Release Information for the 4G Turbo-V Intel® FPGA IP 1.4. 4G Turbo-V Performance and Resource Utilization
2. Designing with the 4G Turbo-V Intel® FPGA IP x
2.1. 4G Turbo-V IP Directory Structure 2.2. Generating a 4G Turbo-V IP 2.3. Simulating a 4G Turbo-V IP
3. 4G Turbo-V Intel® FPGA IP Functional Description x
3.1. 4G Turbo-V Architecture 3.2. 4G Turbo-V Signals and Interfaces 3.3. 4G Turbo-V Timing Diagrams 3.4. 4G Turbo-V Latency and Throughput
3.2. 4G Turbo-V Signals and Interfaces x
Downlink Accelerator Uplink Accelerator 3.2.1. Avalon Streaming Interfaces in DSP Intel FPGA IP
1. About the 4G Turbo-V Intel® FPGA IP
2. Designing with the 4G Turbo-V Intel® FPGA IP
3. 4G Turbo-V Intel® FPGA IP Functional Description
4. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide

3.2. 4G Turbo-V Signals and Interfaces

Downlink Accelerator

Figure 7. Downlink Accelerator Interfaces
Table 5.  Downlink Accelerator Signals
Signal Name Direction Bit Width Description
clk Input 1 300 MHz clock input. All Turbo-V IP interface signals are synchronous to this clock.
reset_n Input 1 Resets the internal logic of whole IP.
sink_valid Input 1 Asserted when data at sink_data is valid. When sink_valid is not asserted, the IP strops processing until sink_valid is reasserted.
sink_data Input 8 Typically carries the bulk of the information being transferred.
sink_sop Input 1 Indicates the start of an incoming packet
sink_eop Input 1 Indicates the end of an incoming packet
sink_ready Output 1 Indicates when the IP can accept data
Sink_error Input 2 Two-bit mask to indicate errors affecting the data transferred in the current cycle.
Crc_enable Input 1 Enables the CRC block
Cb_size_index Input 8 Input code block size K
sink_rm_out_size Input 20 Rate matcher output block size, corresponding to E.
sink_code_blocks Input 15 Soft buffer size for current code block Ncb
sink_rv_idx Input 2 Redundancy version index (0,1,2 or 3)
sink_rm_bypass Input 1 Enables bypass mode in the rate matcher
sink_filler_bits Input 6 The number of filler bits the IP inserts at the transmitter when the IP performs code block segmentation.
source_valid Output 1 Asserted by the IP when there is valid data to output.
source_data Output 24 Carries the bulk of the information transferred. This information is available where valid is asserted.
source_sop Output 1 Indicates the beginning of a packet.
source_eop Output 1 Indicates the end of a packet.
source_ready Input 1 Data reception is valid where the ready signal is asserted.
source_error Output 2

Error signal propagated from Turbo Encoder indicating Avalon-ST protocol violations on source side

• 00: No error

• 01: Missing start of packet

• 10: Missing end of packet

• 11: Unexpected end of packet Other types of errors may also be marked as 11.

Source_blk_size Output 13 Output code block size K

Uplink Accelerator

Figure 8. Uplink Accelerator Interfaces
Table 6.  Uplink Accelerator Signals
Signal Direction Bit Width Description
clk Input 1 300 MHz clock input. All Turbo-V IP interface signals are synchronous to this clock.
reset_n Input 1 Reset of input clock signal
sink_valid Input 1 Avalon streaming input valid
sink_data Input 24 Avalon streaming input data
sink_sop Input 1 Avalon streaming input start of packet
sink_eop Input 1 Avalon streaming input end of packet
sink_ready Input 1 Avalon streaming input ready
conf_valid Input 1 Input configuration conduit valid
cb_size_index Input 8 Block size iteration index
max_iteration Input 5 Maximum iteration
rm_bypass Input 1 Enables bypass mode
sel_CRC24A Input 1

Specifies the type of CRC that you need for the current data block:

• 0: CRC24A

• 1: CRC24B
conf_ready Input 1 Input configuration conduit ready
source_valid Output 1 Avalon streaming output valid
source_data Output 16 Avalon streaming output data
source_sop Output 1 Avalon streaming output start of packet
source_eop Output 1 Avalon streaming output end of packet
source_error Output 2

Error signal indicating Avalon streaming protocol violations on source side:

• 00: No error

• 01: Missing start of packet

• 10: Missing end of packet

• 11: Unexpected end of packet Other types of errors may also be marked as 11.

source_ready Output 1 Avalon streaming output ready
CRC_type Output 1

Indicates the type of CRC that was used for the current data block:

• 0: CRC24A

• 1: CRC24B

source_blk_size Output 13 Specifies the outgoing block size
CRC_pass Output 1

Indicates whether CRC was successful:

• 0: Fail

• 1: Pass

source_iter Output 5 Shows the number of half iterations after which the Turbo decoder stops processing the current data block.

Level Two Title