F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 7/08/2024
Public
Document Table of Contents

3.11.1. PMA and FEC Direct PHY Soft CSR Register Map

The PMA and FEC Direct PHY Soft CSR Register Map allows you to read out the status of the F-Tile PMA/FEC Direct PHY Intel® FPGA IP configuration settings, Avalon® memory-mapped ready signals, PMA ready signals, TX PLL locked and RX CDR lock-to-reference and lock-to-data status signals. It also allows you to control settings for the PMA hard and soft reset signals.

You must enable the Enable datapath Avalon® interface and the Enable Direct PHY soft CSR settings under the Datapath Avalon® Memory-Mapped Interface section in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP parameter editor to access the soft CSR registers. The datapath Avalon® memory-mapped reconfiguration space, starting from offset address 0x800h, contains the F-Tile PMA/FEC Direct PHY Intel® FPGA IP soft CSR registers.