F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 7/08/2024
Public
Document Table of Contents

4.5.2. Guidelines for FGT Reference Clock

For Refclk #i (i = 0 to 9) that you are using for the FGT PMA:
  • When the parameter Refclk #i is active at and after device configuration is set to On, the Refclk #i must be active at and after device configuration time, or else,
    • If you enable Refclk #i monitor, out_refclk_fgt_i does not have a valid output.
    • If you disable Refclk #i monitor, the FGT PMA lane performance degrades.
  • When the parameter Refclk #i is active at and after device configuration is set to Off, the refclk #i can be inactive at any time.
After the Refclk #i becomes active, you must perform a 1'b0 -> 1'b1 transition, otherwise out_refclk_fgt_i does not have a valid output.
After the Refclk #i becomes inactive:
  • If the disable_refclk_monitor_i signal is driven to 1'b1, then you must perform a 1'b1 -> 1'b0 transition, otherwise the FGT PMA lane performance degrades.
  • If the disable_refclk_monitor_i signal is driven to 1'b0 or is disconnected, then you do not have to take any action.