F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 7/08/2024
Public
Document Table of Contents

2.3.1.2. FHT Receiver PMA Architecture

The receiver recovers the clock information from the received serial data, deserializes the high-speed serial data, and creates a parallel data stream for either the receiver Ethernet hard IP, FEC block, or FPGA core.