F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 7/08/2024
Public
Document Table of Contents

3.3.1.2. FGT PMA Configuration Rules for GPON Mode

You can implement the upstream GPON, XG(S)PON, 25G PON, and 50G asymmetric PON protocols with the F-Tile PMA/FEC Direct PHY Intel® FPGA IP by using the settings shown below:
  • Set the FGT PMA configuration rules parameter to GPON.
  • Set the Adaptation mode parameter to manual.
  • Enable the fgt_rx_cdr_fast_freeze_sel port.
  • Enable the fgt_rx_cdr_freeze port.

To achieve the best FGT RX performance when receiving the burst mode traffic, you must adhere to the following guidelines:

  • You must make sure that addresses 0x62000[16] and 0x62004[12] are set to 1’b1.
    Note: 0x62000 and 0x62004 are the offset addresses for lane 0.
  • You must tie the fgt_rx_cdr_fast_freeze_sel signal to 1’b0.
  • The fgt_rx_cdr_freeze signal should assert before/at burst ends, and de-assert after/at burst starts.
    Note: The FGT RX CDR has a good tolerance on the timing relation between fgt_rx_cdr_freeze and rx_serial_data, and you can ignore the transition delay for fgt_rx_cdr_freeze signal from the IP port to the internal CDR control path.
  • During the idle time (no active burst), the differential voltage at the FGT RX should be 0 instead of a negative value. This is to ensure the AC coupling capacitor can quickly charge up to a stable value when the burst arrives.
    • If an optical line terminal (OLT) optical module is connected to FGT RX, then enable squelch should meet the 0 differential voltage requirement.
    • If the FGT TX is connected to FGT RX, then enable TX electrical idle to meet the 0 differential voltage requirement. For PON applications with 32-bit PMA width:
      • To enable TX electrical idle: set the tx_parallel_data bit[35] and bit[75] to 1’b1
      • To disable TX electrical idle: set the tx_parallel_data bit[35] and bit[75] to 1’b0
  • You must manually tune the RX EQ parameters: VGA gain, high frequency boost and DFE data tap 1.
    Note: When the other parameters are fixed, a smaller RX input voltage swing requires a smaller VGA gain value. A larger RX input voltage swing requires a larger VGA gain value.
  • You must manually tune the CDR gain parameters: proportional gain and integral gain.
    • When the fgt_rx_cdr_freeze signal asserts, the integral path is frozen while the proportional path is still active.
    • Higher gain value for the proportional path and integral path helps the RX CDR to realign to the incoming data phase quicker but can create a higher jitter in the process.
    • When the fgt_rx_cdr_freeze signal asserts, a higher gain value for the proportional path may speed up the drifting process and cause the CDR to be far away from the target phase alignment.
    • Proportional gain register is: 0x4157C[24:20].
      Note: This is the offset address for lane 0.
    • Integral gain registers are: 0x4158C[17:13], 0x41484[14:10], 0x41484[24:20], 0x41488[4:0], 0x41488[14:10], 0x41488[24:20], 0x4148C[4:0], 0x4148C[14:10]
      Note: These are the offset addresses for lane 0.
  • An example of optimal settings for the CDR gain registers are:
    • Proportional gain value: 0xA
    • Integral gain value: 0xC