F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/25/2023
Public

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Document Table of Contents

8.3. Transceiver Toolkit Parameter Settings

The following table describes the transceiver toolkit parameter settings.
Table 118.  Transceiver Toolkit Parameter Settings
Parameter Description Control Pane
Auto refresh RX CDR status Enable this option to update the RX CDR status real time. Receiver pane.
Auto refresh RX PMA settings Enable this option to update the RX Equalization settings real time for FGT PMA. Receiver pane.
Auto refresh TX Status Enable this option to update the TX PLL lock status real time. Transmitter pane
Bit error rate (BER) Reports the number of errors divided by bits tested since the last reset of the checker. When RX CDR is locked to reference clock or PRBS checker is not locked, the BER reported is not reliable. Receiver pane
Clear Stats Clear the current number of bits tested, number of error bits and BER. Receiver pane
Hard PRBS checker running

Not Running: checker stops.

Running: checker is checking, and data pattern is locked.

Receiver pane
Hard PRBS generator running

Not Running: generator stops.

Running: generator is sending a pattern.

Transmitter pane
Inject Error Inject a bit error in the transmitter PRBS pattern. Transmitter pane
Line encoding Specifies the modulation type used for serial data. Transmitter and receiver pane
Loopback mode Select the loopbacks mode. The available options are:
  • RX2TXPAR - PMA-receiver-to-transmitter parallel loopback
  • TX2RXPAR - PMA-transmitter-to-receiver parallel loopback
  • TX2RXBUF - PMA-transmitter-to-receiver buffer loopback
Transmitter and receiver pane
Number of bits tested Specifies the number of bits tested since the last reset of the checker. When RX CDR is locked to reference clock or PRBS checker is not locked, the BER reported is not reliable Receiver pane
Number of error bits Specifies the number of error bits encountered since the last reset of the checker. When RX CDR is locked to reference clock or PRBS checker is not locked, the BER reported is not reliable Receiver pane
PRBS locked Locked: indicates the PRBS checker is locked to the received PRBS pattern.

Not Locked: indicates the PRBS checker is not locked to the received PRBS pattern.

Receiver pane
PRBS pattern Select the test pattern for the bit error test. Transmitter and receiver pane
RX CDR locked to ref clock Locked: Indicates the receiver CDR is in lock-to-reference (LTR) mode.

Not Locked: Indicates the receiver CDR is not locked to reference clock.

Don't Care: When the receiver CDR is in LTD mode.

Receiver pane
RX CDR locked to data Locked: Indicates the receiver CDR is in lock-to-data (LTD) mode.

Not Locked: Indicates the receiver CDR is not locked to incoming data.

Receiver pane
RX Enable Gray Code Enables Gray coding for PAM4 only. Receiver pane
RX PMA Settings RX Equalization settings. Receiver pane
RX Polarity Inversion Enable RX polarity inversion. Receiver pane
RX Ready Ready: RX channel out of reset and CDR locks to data.

Not Ready: RX channel in reset or CDR is not locked to data.

Receiver pane
RX Reset FGT PMA Reset the FGT RX datapath.
Note: Clicking the RX reset of one channel resets all the RX channels in the same F-Tile PMA/FEC Direct PHY Intel® FPGA IP instance.
Receiver pane
Start Starts the pattern generator or checker on the channel to verify incoming data. Transmitter and receiver pane
Stop Stops generating patterns and testing the channel. Transmitter and receiver pane
TX Enable Gray Code Enables Gray coding for PAM4 only. Transmitter pane
TX Equalization Parameters FGT 42 FHT 43 44 Transmitter pane and receiver pane

Post_tap_1

Main_tap

Pre_tap_1

Pre_tap_2

C-3: Pre-cursor 3

C-2: Pre-cursor 2

C-1: Pre-cursor 1

C0: Main cursor

C+1: Post-cursor 1

C+2: Post-cursor 2

C+3: Post-cursor 3

C+4: Post-cursor 4

TX PLL Locked Locked: Indicates TX PLL locks to reference clock. Transmitter pane
TX Polarity Inversion Enable TX polarity inversion. Transmitter pane
TX Reset FGT PMA Reset the FGT TX PMA datapath.
Note: Clicking the TX reset of one channel resets all the TX channels in the same F-Tile PMA/FEC Direct PHY Intel® FPGA IP instance.
Transmitter pane
42 Refer to F-Tile TX Equalizer Tool for legal settings.
43 Refer to FHT PMA Architecture for legal settings.
44 When internal serial loopback is enabled, the TX Equalization Parameters are set to default values.