F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/25/2023
Public

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3.6.4. FGT PMA Fractional Mode

For a given data rate, the drop-down menu lists the supported integer mode reference clock frequencies. For a given data rate, if the required reference clock frequency is not listed in the drop-down, you can either select one of the supported integer mode reference clock frequencies or enable fractional mode.

  • When enabling fractional mode, if exact fraction is not available (K = 0.25,0.5, 0.75), use 140MHz reference clock frequency for approximate fractional mode.
  • To calculate K, divide k counter displayed in the IP GUI system messages; K = k / 2^22. For example, for k = 2097152, K = 0.5.
  • For a given data rate, you must enable fractional mode if you need to dynamically configure the K value during run time. When you enable fractional mode, you must enter the TX FGT PLL fractional mode reference clock frequency.

FGT PMA supports fractional mode in following PMA modes:

Table 71.  FGT PMA Support for Fractional Mode
PMA Mode Fractional Mode Support
TX simplex TX FGT PLL supports fractional mode in TX simplex. To enable, select TX simplex option for PMA mode, and turn on the Enable TX FGT PLL fractional mode in the parameter editor. The TX PLL fractional counter values automatically calculate for the selected reference clock frequency. You can place TX Simplex fractional mode on any of 16 FGT TX PMAs.
Note: FGT PMA does not support fractional mode for RX simplex.
Duplex FGT PMA in Duplex PMA mode supports fractional mode. To enable fractional mode in duplex PMA mode, select the Duplex option for PMA mode, select up to 16 for the Number of PMA lanes, and turn on Enable TX FGT PLL fractional mode option in the parameter editor.
  • In Duplex fractional mode, the output of each TX PLL is used as the reference clock for corresponding RX CDR. Each TX PLL is configured as fractional mode.
  • A separate reference clock is not required for RX CDR. TX PLL fractional counter values, and RX CDR reference clock frequency, automatically calculate for the selected reference clock frequency. You can leave the rx_cdr_refclk_link port unconnected and it is tied to ground internally in the IP core.
  • You can place duplex fractional mode on any of 16 FGT PMAs.
Primary PLL configuration To enable fractional mode with the primary PLL configuration, select the Duplex option for PMA mode, select 2 or 4 for the Number of PMA lanes, and turn on Enable TX FGT PLL fractional mode and Enable TX FGT PLL cascade mode options in the parameter editor.
  • In Primary PLL configuration, the TX PLL of one lane is in fractional mode and acts as the reference clock source for the local CDR and TX PLL and RX CDR blocks of other lanes (configured in integer mode) within the quad.
  • Primary PLL configuration is not supported when you select 6 ,8, 12, or 16 for the number of PMA lanes.
  • You can place the primary PLL configuration with 2 PMA lanes either on FGT PMA Lane 1 and 0 (same quad) of any quad, with Lane 1 as the primary. On FGT PMA Lane 3 and 2 (same quad) of any quad with lane 3 being the primary.
  • You can place the primary PLL configuration with 4 PMA lanes on FGT PMA Lane 3,2,1 and 0 (same quad) of any quad with Lane 3 being the primary.
  • When you place any primary PLL configuration in Quad 2, you cannot configure reference clock [8] (accessible by Quad2) as output to provide RX recovered clock.
  • When you place any primary PLL configuration in Quad 3, you cannot configure reference clock [9] (accessible by Quad3) as output to provide RX recovered clock.
Note: Refer to FGT PLL Configuration in F-tile Architecture User Guide for more information.

Tuning the Fractional Value in Fractional Mode

You can configure the F-tile FGT PMA to:
  • Transmit serial data.
  • Generate a clock for FPGA core fabric.
You can configure the FGT PMA in fractional mode to adjust the frequency and datarate by a small amount (+/- 1000 ppm) for rate matching purposes. In order to meet the jitter specifications of OTN (Optical Transport Network) and SDI (Serial Digital Interface), dynamic changes in the fractional value should have the following limits:
  • Maximum step size: 30 KHz
  • Minimum duration between steps: 1 us
For example, if a 12 GHz clock needs to adjust 25 ppm, the maximum step size is 30 KHz / 12 GHz * 10^6 = 2.5 ppm. You need to perform at least 10 discrete steps, where each step is at most 2.5 ppm and the duration in between should be at least 1 us.
If the OTN or SDI jitter specifications does not apply to your design, and you want to adjust the data rate without losing lock, then dynamic changes in the fractional value should have the following limits:
  • Maximum step size: 100 ppm
  • Minimum duration between steps: unknown
Intel recommends keeping the duration as long as you can afford to get stable performance.
If the design needs to fundamentally change the data rate by more than ± 100 ppm, you need to:
  1. Hold the PLL in reset.
  2. Change the k counter and M counter.
  3. Release the PLL reset.

Each FGT PMA has an Avalon® memory-mapped interface register containing the k counter. The k counter / 2^22 gives the fractional value K of the feedback counter. The fractional value K plus the M counter value provides the total feedback counter and determines how much PPM each bit in the k counter represents. For example, the LSB (least significant bit) in the k counter represents PPM = (1 / 2^22) / (K+M) × (10^6).

The procedure to change the k counter is:

  1. Change the k counter to the new value.
  2. Pulse the strobe bit 0 -> 1-> 0 to lock in the new k counter.

Each FGT PMA contains 3 PLLs; slow, medium and fast. FGT PMAs are organized in a quad. The k counter and strobe bit Avalon® memory-mapped interface register addresses depend on the location of the transceiver in the quad and which PLL is used (slow, medium, fast) as shown in the table below.

Table 72.  FGT PMA Fractional k Counter and Strobe Register Addresses
Channel Location in Quad PLL Fractional k Counter Register Strobe Register
0 Slow 0x44000[30:9] 0x4400C[17]
Medium 0x44100[30:9] 0x4410C[17]
Fast 0x44200[30:9] 0x4420C[17]
1 Slow 0x4C000[30:9] 0x4C00C[17]
Medium 0x4C100[30:9] 0x4C10C[17]
Fast 0x4C200[30:9] 0x4C20C[17]
2 Slow 0x54000[30:9] 0x5r00C[17]
Medium 0x54100[30:9] 0x5410C[17]
Fast 0x54200[30:9] 0x5420C[17]
3 Slow 0x5C000[30:9] 0x5C00C[17]
Medium 0x5C100[30:9] 0x5C10C[17]
Fast 0x5C200[30:9] 0x5C20C[17]
You can find the transceiver location and PLL selected in the <design_name>.syn.rpt generated by the Intel® Quartus® Prime Pro Edition software as shown in the following figure.
Figure 77. Sample Intel® Quartus® Prime Pro Edition Software Synthesis Compilation Result
; z1577a_u_ux_quad_3__ux3_synth_lc_med_en         ; enable                                   ; String        ;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_out_hz           ; 0000000001010110011011010011111010000000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_pfd_hz           ; 0000000000000000000000000000000000000000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_ref_hz           ; 0000000000001000110110011110111000100000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_rx_postdiv_hz    ; 0000000000010001010010010000110010000000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_tx_postdiv_hz    ; 0000000000000110111010100000010100000000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_vco_hz           ; 0000001010110011011010011111010000000000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_fractional_en      ; enable                                   ; String         ;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_k_counter          ; 0000111010100111001110                   ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_l_counter          ; 001000                                   ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_m_counter          ; 000100111                                ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_n_counter          ; 000001                                   ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_powerdown_mode     ; false                                    ; String         ;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_primary_use        ; ux3_synth_lc_med_primary_use_disabled    ; String         ;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_rx_postdiv_counter ; 00101000                                 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_tx_postdiv_counter ; 01100100                                 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_tx_postdiv_fractional_en ; disable                            ; String         ;
In the sample compilation result shown above, the FGT PMA is placed in quad 3, channel 3 and the medium PLL is used. The M counter is 39 (000100111) and the nominal K value is 0.057 (0000111010100111001110/2^22). The LSB in the k counter represents 6 ppb (parts per billion) (1/2^22/39.057). The k counter register address is 0x5C100[30:9] and the strobe register bit address is 0x5C10C[17].