AN 784: Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices

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ID 683856
Date 9/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices A. Reference Design Files
1. Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Compiling the Reference Design 1.5. Testing the Reference Design 1.6. Extending the Reference Design with Custom Persona 1.7. Document Revision History for AN 784: Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping 1.1.3. Floorplanning
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Installing the Intel® Arria® 10 GX FPGA Development Kit 1.2.3. Installing the Linux Driver 1.2.4. Bringing Up the Reference Design
1.3. Reference Design Components x
1.3.1. BSP Top
1.3.1. BSP Top x
1.3.1.1. PCI Express* IP core 1.3.1.2. Intel® Arria® 10 DDR4 External Memory Interfaces IP Core 1.3.1.3. Design Top
1.3.1.3. Design Top x
1.3.1.3.1. Global Reset Logic 1.3.1.3.2. PR Region Wrapper 1.3.1.3.3. Intel® Arria® 10 Partial Reconfiguration Region Controller IP Core 1.3.1.3.4. Partial Reconfiguration Logic
1.5. Testing the Reference Design x
1.5.1. program_fpga_jtag 1.5.2. fpga-configure example_host_uio
example_host_uio x
1.5.3.1. Compiling the Example Applications 1.5.3.2. Programming the Design Using Example Applications
1. Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
A. Reference Design Files

1.5.3.2. Programming the Design Using Example Applications

The following steps describe programming your design using the provided scripts:

  1. To program the DDR access persona’s .sof file after design compilation, type the following from the Linux shell: 
    program-fpga-jtag -f=a10_pcie_devkit_cvp_ddr4_access.sof -c=1 -i=1
  2. To verify the functionality of the design, type the following from the Linux shell: 
    ./example_host_uio
  3. To program the basic DSP persona’s .rbf file after design compilation, type the following from the Linux shell: 
    fpga-configure -p a10_pcie_devkit_cvp_basic_dsp.pr_partition.rbf 10000
  4. To verify the functionality of the design, type the following from the Linux shell: 
    ./example_host_uio
  5. To program the basic arithmetic persona’s .rbf file after design compilation, type the following from the Linux shell: 
    fpga-configure -p a10_pcie_devkit_cvp_basic_arithmetic.pr_partition.rbf 10000
  6. To verify the functionality of the design, type the following from the Linux shell: 
    ./example_host_uio
  7. To program the Game of Life persona's .rbf file after design compilation, type the following from the Linux shell: 
    fpga-configure -p a10_pcie_devkit_cvp_gol.pr_partition.rbf 10000
  8. To verify the functionality of the design, type the following from the Linux shell: 
    ./example_host_uio -v
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