AN 784: Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices

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ID 683856
Date 9/24/2018
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Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices A. Reference Design Files
1. Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Compiling the Reference Design 1.5. Testing the Reference Design 1.6. Extending the Reference Design with Custom Persona 1.7. Document Revision History for AN 784: Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping 1.1.3. Floorplanning
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Installing the Intel® Arria® 10 GX FPGA Development Kit 1.2.3. Installing the Linux Driver 1.2.4. Bringing Up the Reference Design
1.3. Reference Design Components x
1.3.1. BSP Top
1.3.1. BSP Top x
1.3.1.1. PCI Express* IP core 1.3.1.2. Intel® Arria® 10 DDR4 External Memory Interfaces IP Core 1.3.1.3. Design Top
1.3.1.3. Design Top x
1.3.1.3.1. Global Reset Logic 1.3.1.3.2. PR Region Wrapper 1.3.1.3.3. Intel® Arria® 10 Partial Reconfiguration Region Controller IP Core 1.3.1.3.4. Partial Reconfiguration Logic
1.5. Testing the Reference Design x
1.5.1. program_fpga_jtag 1.5.2. fpga-configure example_host_uio
example_host_uio x
1.5.3.1. Compiling the Example Applications 1.5.3.2. Programming the Design Using Example Applications
1. Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
A. Reference Design Files

1.1.2. Memory Address Mapping

The PCIe* IP core connects to the design core through two Avalon® -MM master interfaces. These Avalon® -MM master interfaces are base address registers (BARs), BAR 2 and BAR 4.

BAR 2 connects the PR driver to the following components:
  • The PR IP core
  • The system description ROM
The BAR 4 Avalon® -MM connects to the following components:
  • The freeze bridges
  • The PR region controller
  • Up to 8 kilobytes (KB) of memory in the PR region
The following table lists the memory address mapping for the PCIe* IP core:
Table 1.   PCIe* Memory Address Map
Domain Address Map Base End
BAR 2 System Description ROM 0x0000_0000 0x0000_0FFF
BAR 2 PR IP 0x0000_1000 0x0000_103F
BAR 4 PR Region 0x0000_0000 0x0000_FFFF
BAR 4 PR Region Controller 0x0001_0000 0x0001_000F
BAR 4 DDR4 Calibration Export 0x0001_0010 0x0001_001F

The EMIF IP provides status on DDR4 calibration. During initialization, the EMIF IP performs training to reset the DDR4 interface. The EMIF calibration flag reports the training success or the failure to the host. The host takes the necessary action in the event of a DDR4 training failure.

The following table lists the memory address mapping from the EMIF IP to the PR logic:
Table 2.  DDR4 External Memory Interfaces (EMIF) Memory Address Map
Address Map Base End
DDR 0x0000_0000 0x7fff_ffff
The PR logic accesses the 2 gigabyte (GB) DDR4 memory space using an Avalon® -MM master interface.
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