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1.1. Reference Design Overview
1.2. Getting Started
1.3. Reference Design Components
1.4. Compiling the Reference Design
1.5. Testing the Reference Design
1.6. Extending the Reference Design with Custom Persona
1.7. Document Revision History for AN 784: Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
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1.3.1.2. Intel® Arria® 10 DDR4 External Memory Interfaces IP Core
The ddr4_emif logic includes the Intel® Arria® 10 External Memory Interfaces IP core. This IP core interfaces to the DDR4 external memory, with a 64-bit interface that runs at 1066.0 MHz. Also, the IP core provides 2 GB of DDR4 SDRAM memory space. The EMIF Avalon® -MM slave runs at 300 MHz.
The following table lists the Intel® Arria® 10 External Memory Interfaces IP parameters that are different from the Intel® Arria® 10 GX FPGA Development Kit with DDR4 HILO preset settings:
Setting | Parameter | Value |
---|---|---|
Memory - Topology | DQ width | 64 |
DQ pins per DQS group | 8 | |
Number of DQS groups | 8 | |
Alert# pin placement | I/O Lane with Address/Command Pins | |
Address/Command I/O lane of ALERT# | 3 | |
Pin index of ALERT# | 0 |