AN 784: Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices

ID 683856
Date 9/24/2018
Public
Document Table of Contents

1.3.1.2. Intel® Arria® 10 DDR4 External Memory Interfaces IP Core

The ddr4_emif logic includes the Intel® Arria® 10 External Memory Interfaces IP core. This IP core interfaces to the DDR4 external memory, with a 64-bit interface that runs at 1066.0 MHz. Also, the IP core provides 2 GB of DDR4 SDRAM memory space. The EMIF Avalon® -MM slave runs at 300 MHz.

The following table lists the Intel® Arria® 10 External Memory Interfaces IP parameters that are different from the Intel® Arria® 10 GX FPGA Development Kit with DDR4 HILO preset settings:

Table 4.   Intel® Arria® 10 DDR4 External Memory Interfaces IP Configuration
Setting Parameter Value
Memory - Topology DQ width 64
DQ pins per DQS group 8
Number of DQS groups 8
Alert# pin placement I/O Lane with Address/Command Pins
Address/Command I/O lane of ALERT# 3
Pin index of ALERT# 0