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1.1. Reference Design Overview
1.2. Getting Started
1.3. Reference Design Components
1.4. Compiling the Reference Design
1.5. Testing the Reference Design
1.6. Extending the Reference Design with Custom Persona
1.7. Document Revision History for AN 784: Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
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1.3.1.1. PCI Express* IP core
The Intel® Arria® 10 Hard IP for PCI Express* IP core is Gen3x8 with a 256-bit interface, running at 250 MHz.
The following table provides information on the PCI Express* IP parameters that the reference design uses that are different from the default settings:
Setting | Parameter | Value |
---|---|---|
System Settings | Application interface type | Avalon-MM with DMA |
Hard IP mode | Gen3:x8, Interface: 256-bit, 250 MHz | |
Port type | Native endpoint | |
RX buffer credit allocation for received requests vs completions | Low | |
Avalon-MM Settings | Enable control register access (CRA) Avalon-MM slave port | Disable |
Base Address Registers - BAR2 | Type | 32-bit non-prefetchable memory |
Base Address Registers - BAR4 | Type | 32-bit non-prefetchable memory |
Device Identification Registers | Vendor ID | 0x00001172 |
Device ID | 0x00005052 | |
Revision ID | 0x00000001 | |
Class code | 0x00ea0001 | |
Subsystem Vendor ID | 0x00001172 | |
Subsystem Device ID | 0x00000001 | |
PCI Express/PCI Capabilities - Device | Maximum payload size | 256 Bytes |
Configuration, Debug, and Extension Options | Enable Intel® Arria® 10 GX FPGA Development Kit Connection | Enable |
PHY Characteristics | Requested equalization far-end TX preset | Preset 9 |
Note: Instantiate the PCI Express* IP core as part of a Platform Designer system.