AN 784: Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices

ID 683856
Date 9/24/2018
Public
Document Table of Contents

1.3.1. BSP Top

This Platform Designer system contains all the subsystems of this reference design. The system comprises the following three main components:
  • The top-level design
  • The PCIe* IP
  • The DDR4 EMIF IP
The system connects to external pins through the a10_pcie_ref_design.sv wrapper.