AN 784: Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices

ID 683856
Date 9/24/2018
Public
Document Table of Contents

1.3.1.3.3. Intel® Arria® 10 Partial Reconfiguration Region Controller IP Core

Use the Intel® Arria® 10 Partial Reconfiguration Region Controller IP core to initiate a freeze request to the PR region. The PR region finalizes any actions, on freeze request acknowledgment. The freeze bridges also intercept the Avalon-MM interfaces to the PR region, and correctly responds to any transactions made to the PR region during partial reconfiguration. Finally, on PR completion, the region controller issues a stop request, allowing the region to acknowledge, and act accordingly. The fpga-region-controller program provided with this reference design performs these functions.

The reference design configures the Partial Reconfiguration Region Controller IP core to operate as an internal host. The design connects this IP core to the PCI Express* IP core, via an instance of the Avalon-MM interface. The PR IP core has a clock-to-data ratio of 1. Therefore, the PR IP core is not capable of handling encrypted or compressed PR data.

The following table lists the configuration fields of the Intel® Arria® 10 Hard IP for PCI Express* IP core that are different from the preset settings:

Parameters Value
Enable JTAG debug mode Disable
Enable Avalon-MM slave interface Enable
Input data width 32