AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

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ID 683844
Date 5/04/2015
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Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit x
1.1. Reference Design Overview 1.2. Hardware and Software Requirements 1.3. Hardware Setup 1.4. System Modules 1.5. Reference Design Files 1.6. Generating Programming File 1.7. Top Level HDL Parameters 1.8. Setting Up the Software Command Line Environment 1.9. User Commands 1.10. Dynamic Reconfiguration 1.11. Customize the C code 1.12. AN 729 Document Revision History
1.4. System Modules x
1.4.1. Qsys System
1.4.1. Qsys System x
1.4.1.1. JESD204B Subsystem 1.4.1.2. Nios II Subsystem
1.4.1.1. JESD204B Subsystem x
1.4.1.1.1. Configuring the JESD204B IP core parameters in QSYS 1.4.1.1.2. Reset Sequencer 1.4.1.1.3. Transceiver PHY Reset Controller and ATX PLL 1.4.1.1.4. JESD204B Subsystem Address Map
1.4.1.2. Nios II Subsystem x
1.4.1.2.1. Nios II Subsystem Address Map
1.5. Reference Design Files x
1.5.1. FPGA Pin Assignments
1.10. Dynamic Reconfiguration x
1.10.1. Data Rate Reconfiguration
1.10.1. Data Rate Reconfiguration x
1.10.1.1. Customizing the Data Rate Reconfiguration Parameters
1.11. Customize the C code x
1.11.1. Sub Functions in main.c Source File 1.11.2. Functions in rules.c Source File 1.11.3. Custom Peripheral Access Macros in macros.c Source File
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit

1.7. Top Level HDL Parameters

The top level HDL file (jesd204b_ed.sv) located in the <project directory>/jesd204b_nios_ref_design/jesd204b_ed/ directory includes project parameters that define the configuration of the reference design as a whole. The parameters are described in the table below.

Table 9.   Top Level Parameters
Parameter Description
LINK Number of JESD204B links. Set to match the configuration in QSYS.
L Number of JESD204B lanes per converter device. Set to match the configuration in QSYS.
M Number of JESD204B converters per device. Set to match the configuration in QSYS.
F Number of JESD204B octets per frame. Set to match the configuration in QSYS.
N Number of JESD204B conversion bits per converter device. Set to match the configuration in QSYS.
N_PRIME Number of JESD204B transmitted bits per sample. Set to match the configuration in QSYS.
S Number of JESD204B transmitted samples per converter device per frame. Set to match the configuration in QSYS.
CS Number of JESD204B control bits per conversion sample. Set to match the configuration in QSYS.
F1_FRAMECLK_DIV Divider ratio for frame_clk when F=1. Refer to the JESD204B IP Core User Guide for more details.
F2_FRAMECLK_DIV Divider ratio for frame_clk when F=2. Refer to the JESD204B IP Core User Guide for more details.
POLYNOMIAL_LENGTH Defines the polynomial length for the PRBS pattern generator and checker. Refer to the JESD204B IP Core User Guide for more details.
FEEDBACK_TAP Defines the feedback tap for the PRBS pattern generator and checker. Refer to the JESD204B IP Core User Guide for more details.
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