AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

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ID 683844
Date 5/04/2015
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Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit x
1.1. Reference Design Overview 1.2. Hardware and Software Requirements 1.3. Hardware Setup 1.4. System Modules 1.5. Reference Design Files 1.6. Generating Programming File 1.7. Top Level HDL Parameters 1.8. Setting Up the Software Command Line Environment 1.9. User Commands 1.10. Dynamic Reconfiguration 1.11. Customize the C code 1.12. AN 729 Document Revision History
1.4. System Modules x
1.4.1. Qsys System
1.4.1. Qsys System x
1.4.1.1. JESD204B Subsystem 1.4.1.2. Nios II Subsystem
1.4.1.1. JESD204B Subsystem x
1.4.1.1.1. Configuring the JESD204B IP core parameters in QSYS 1.4.1.1.2. Reset Sequencer 1.4.1.1.3. Transceiver PHY Reset Controller and ATX PLL 1.4.1.1.4. JESD204B Subsystem Address Map
1.4.1.2. Nios II Subsystem x
1.4.1.2.1. Nios II Subsystem Address Map
1.5. Reference Design Files x
1.5.1. FPGA Pin Assignments
1.10. Dynamic Reconfiguration x
1.10.1. Data Rate Reconfiguration
1.10.1. Data Rate Reconfiguration x
1.10.1.1. Customizing the Data Rate Reconfiguration Parameters
1.11. Customize the C code x
1.11.1. Sub Functions in main.c Source File 1.11.2. Functions in rules.c Source File 1.11.3. Custom Peripheral Access Macros in macros.c Source File
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit

1.5.1. FPGA Pin Assignments

The top level signals with its corresponding FPGA pin assignments on the Arria 10 FPGA development board are listed in the table below.

Table 8.  Top Level Signals and the Corresponding FPGA Pins
Top Level Signal Name FPGA Pin Number I/O Standard Direction
global_rst_n T12 1.8 V Input
device_clk W8 LVDS Input
device_clk (n) W7 LVDS Input
mgmt_clk BD32 1.8 V Input
sma_clkout E24 1.8 V Output
spi_MISO A17 1.8 V Input
spi_MOSI F18 1.8 V Output
spi_SCLK G18 1.8 V Output
spi_SS_n[0] G21 1.8 V Output
tx_serial_data[3] Y1 High speed differential I/O Output
tx_serial_data[3] (n) Y2 High speed differential I/O Output
tx_serial_data[2] AB1 High speed differential I/O Output
tx_serial_data[2] (n) AB2 High speed differential I/O Output
tx_serial_data[1] V1 High speed differential I/O Output
tx_serial_data[1] (n) V2 High speed differential I/O Output
tx_serial_data[0] T1 High speed differential I/O Output
tx_serial_data[0] (n) T2 High speed differential I/O Output
rx_serial_data[3] W3 High speed differential I/O Input
rx_serial_data[3] (n) W4 High speed differential I/O Input
rx_serial_data[2] AA3 High speed differential I/O Input
rx_serial_data[2] (n) AA4 High speed differential I/O Input
rx_serial_data[1] Y5 High speed differential I/O Input
rx_serial_data[1] (n) Y6 High speed differential I/O Input
rx_serial_data[0] V5 High speed differential I/O Input
rx_serial_data[0] (n) V6 High speed differential I/O Input
sysref_out J19 LVDS Output
sysref_out (n) K19 LVDS Output
sync_n_out C15 LVDS Output
sync_n_out (n) B15 LVDS Output
Level Two Title