AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

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ID 683844
Date 5/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit x
1.1. Reference Design Overview 1.2. Hardware and Software Requirements 1.3. Hardware Setup 1.4. System Modules 1.5. Reference Design Files 1.6. Generating Programming File 1.7. Top Level HDL Parameters 1.8. Setting Up the Software Command Line Environment 1.9. User Commands 1.10. Dynamic Reconfiguration 1.11. Customize the C code 1.12. AN 729 Document Revision History
1.4. System Modules x
1.4.1. Qsys System
1.4.1. Qsys System x
1.4.1.1. JESD204B Subsystem 1.4.1.2. Nios II Subsystem
1.4.1.1. JESD204B Subsystem x
1.4.1.1.1. Configuring the JESD204B IP core parameters in QSYS 1.4.1.1.2. Reset Sequencer 1.4.1.1.3. Transceiver PHY Reset Controller and ATX PLL 1.4.1.1.4. JESD204B Subsystem Address Map
1.4.1.2. Nios II Subsystem x
1.4.1.2.1. Nios II Subsystem Address Map
1.5. Reference Design Files x
1.5.1. FPGA Pin Assignments
1.10. Dynamic Reconfiguration x
1.10.1. Data Rate Reconfiguration
1.10.1. Data Rate Reconfiguration x
1.10.1.1. Customizing the Data Rate Reconfiguration Parameters
1.11. Customize the C code x
1.11.1. Sub Functions in main.c Source File 1.11.2. Functions in rules.c Source File 1.11.3. Custom Peripheral Access Macros in macros.c Source File
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit

1.10.1.1. Customizing the Data Rate Reconfiguration Parameters

To customize the design to support a different transceiver configuration, follow the steps below:

  1. Follow the steps in the JESD204B Subsystem section to open the jesd204b_subsystem module and enter your desired serial data rate in the Data Rate box.
  2. Turn on the Enable Transceiver Dynamic Reconfiguration option. On the File menu, select Save to save the settings.
  3. Click the Generate HDL button on the bottom right corner of the Qsys window.
    In addition to generating the Qsys system HDL, Qsys also generates the transceiver configuration data stored as an array in a C header file.
  4. After Qsys is done generating the HDL, click the Finish button on the bottom right corner of the Qsys window.
  5. In your shell, navigate to the Qsys-generated C header file location: <project directory>/jesd204b_nios_ref_design/jesd204b_ed/jesd204b_ed_qsys/altera_xcvr_native_a10_141/synth/reconfig/altera_xcvr_native_a10_reconfig_parameters.h.
  6. Open the altera_xcvr_native_a10_reconfig_parameters.h file and copy the array 'unsigned int altera_xcvr_native_a10_ram_array[120] = {…}'
  7. Navigate to the project transceiver reconfiguration parameters header file location: <project directory>/jesd204b_nios_ref_design/jesd204b_ed/software/jesd204_nios_ed/altera_xcvr_native_a10_reconfig_parameters.h.
  8. Paste the array 'unsigned int altera_xcvr_native_a10_ram_array[120] = {…}' and rename the array to 'unsigned int altera_xcvr_native_a10_ram_array_1[120] = {…}'
  9. Repeat steps 1-8 above, this time entering the original data rate divided by 2 in the Data Rate option of the JESD204B IP parameter editor window in Qsys. Be aware of the minimum data rate limits of the JESD204B IP core that is targeted to the device family of your choice. Refer to the JESD204B IP Core User Guide for the latest information on the minimum serial data rate specification. Qsys generates the configuration data array representing the new data rate. Copy and paste the data array unsigned int altera_xcvr_native_a10_ram_array[120] = {…} from the <project directory>/jesd204b_nios_ref_design/jesd204b_ed/jesd204b_ed_qsys/altera_xcvr_native_a10_141/synth/reconfig/altera_xcvr_native_a10_reconfig_parameters.h header file to the <project directory>/jesd204b_nios_ref_design/jesd204b_ed/software/jesd204_nios_ed/altera_xcvr_native_a10_reconfig_parameters.h header file as ‘unsigned int altera_xcvr_native_a10_ram_array_2[120] = {…}'
  10. Repeat steps 1-8 above, this time entering the original data rate divided by 4 in the Data Rate option of the JESD204B IP parameter editor window in Qsys. Be aware of the minimum data rate limits of the JESD204B IP core that is targeted to the device family of your choice. Refer to the JESD204B IP Core User Guide for the latest information on the minimum serial data rate specification. Qsys generates the configuration data array representing the new data rate. Copy and paste the data array unsigned int altera_xcvr_native_a10_ram_array[120] = {…} from the <project directory>/jesd204b_nios_ref_design/jesd204b_ed/jesd204b_ed_qsys/altera_xcvr_native_a10_141/synth/reconfig/altera_xcvr_native_a10_reconfig_parameters.h header file to the <project directory>/jesd204b_nios_ref_design/jesd204b_ed/software/jesd204_nios_ed/altera_xcvr_native_a10_reconfig_parameters.h header file as ‘unsigned int altera_xcvr_native_a10_ram_array_4[120] = {…}'
  11. Repeat steps 1-10 above for the ATX PLL module (xcvr_atx_pll_a10_0). Make sure to turn on the Generate C header file option under the Dynamic Reconfiguration tab of the ATX PLL parameter editor window in QSYS.
    The Qsys-generated C header file is found in location: <project directory>/jesd204b_nios_ref_design/jesd204b_ed/jesd204b_ed_qsys/altera_xcvr_atx_pll_a10_141/synth/reconfig/altera_xcvr_atx_pll_a10_reconfig_parameters.h. The ATX PLL reconfiguration data array is named 'unsigned int altera_xcvr_atx_pll_a10_ram_array[11] = {…}'. The project ATX PLL reconfiguration parameters header file location is: <project directory>/jesd204b_nios_ref_design/jesd204b_ed/software/jesd204_nios_ed/altera_xcvr_atx_pll_a10_reconfig_parameters.h. Rename the data arrays appropriately when copying between the two header file locations.
  12. Repeat step 11 for the number of ATX PLL modules that are present in your design.

The steps above illustrate how you can customize your code to support the existing data rate reconfiguration function (for example, reconfigure to data rate divided by 2 and by 4) using an initially configured data rate of your choice. Modify the C code to further customize your code to support arbitrary data rate changes and even different transceiver configurations (refer to the Customize the C code section).

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