AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

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ID 683844
Date 5/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit x
1.1. Reference Design Overview 1.2. Hardware and Software Requirements 1.3. Hardware Setup 1.4. System Modules 1.5. Reference Design Files 1.6. Generating Programming File 1.7. Top Level HDL Parameters 1.8. Setting Up the Software Command Line Environment 1.9. User Commands 1.10. Dynamic Reconfiguration 1.11. Customize the C code 1.12. AN 729 Document Revision History
1.4. System Modules x
1.4.1. Qsys System
1.4.1. Qsys System x
1.4.1.1. JESD204B Subsystem 1.4.1.2. Nios II Subsystem
1.4.1.1. JESD204B Subsystem x
1.4.1.1.1. Configuring the JESD204B IP core parameters in QSYS 1.4.1.1.2. Reset Sequencer 1.4.1.1.3. Transceiver PHY Reset Controller and ATX PLL 1.4.1.1.4. JESD204B Subsystem Address Map
1.4.1.2. Nios II Subsystem x
1.4.1.2.1. Nios II Subsystem Address Map
1.5. Reference Design Files x
1.5.1. FPGA Pin Assignments
1.10. Dynamic Reconfiguration x
1.10.1. Data Rate Reconfiguration
1.10.1. Data Rate Reconfiguration x
1.10.1.1. Customizing the Data Rate Reconfiguration Parameters
1.11. Customize the C code x
1.11.1. Sub Functions in main.c Source File 1.11.2. Functions in rules.c Source File 1.11.3. Custom Peripheral Access Macros in macros.c Source File
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit

1.3. Hardware Setup

  1. Install the ADI AD9680 converter card module to the FMC port B (J2) on the Arria 10 FPGA development board.
  2. Connect the mini-USB cable to the mini-USB connector (J3) on the development board.
  3. Connect the power adapter shipped with the development board to the power supply jack (J13).
  4. Connect the AD9516 power adapter to the power supply jack on the AD9516 clock module card.
  5. Connect the USB cable from your workstation to the USB connector on the AD9516 card.
  6. Connect the AD9516 clock module OUT0 SMA connector (J0A) to the CLKIN SMA connector (J801) on the AD9680 card.
  7. Connect the AD9516 clock module OUT8 SMA connector (J8A) to the Refclk to FPGA SMA connector (J804) on the AD9680 card.
  8. Turn on the power for the AD9516 clock module card.
  9. Configure the clock settings of the AD9516 to output 614.4 MHz clock for the ADCs at OUT0 SMA connector and 153.6 MHz for the FPGA at OUT8 SMA connector. Refer to the AD9516 documentation for more information on configuring the AD9516 clock module.
  10. Turn on the power for the Arria 10 FPGA development board.

The hardware system is now ready for programming. Refer to instructions in the Generating Programming File section on how to generate and download the programming file onto the FPGA.

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