AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor

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ID 683844
Date 5/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit x
1.1. Reference Design Overview 1.2. Hardware and Software Requirements 1.3. Hardware Setup 1.4. System Modules 1.5. Reference Design Files 1.6. Generating Programming File 1.7. Top Level HDL Parameters 1.8. Setting Up the Software Command Line Environment 1.9. User Commands 1.10. Dynamic Reconfiguration 1.11. Customize the C code 1.12. AN 729 Document Revision History
1.4. System Modules x
1.4.1. Qsys System
1.4.1. Qsys System x
1.4.1.1. JESD204B Subsystem 1.4.1.2. Nios II Subsystem
1.4.1.1. JESD204B Subsystem x
1.4.1.1.1. Configuring the JESD204B IP core parameters in QSYS 1.4.1.1.2. Reset Sequencer 1.4.1.1.3. Transceiver PHY Reset Controller and ATX PLL 1.4.1.1.4. JESD204B Subsystem Address Map
1.4.1.2. Nios II Subsystem x
1.4.1.2.1. Nios II Subsystem Address Map
1.5. Reference Design Files x
1.5.1. FPGA Pin Assignments
1.10. Dynamic Reconfiguration x
1.10.1. Data Rate Reconfiguration
1.10.1. Data Rate Reconfiguration x
1.10.1.1. Customizing the Data Rate Reconfiguration Parameters
1.11. Customize the C code x
1.11.1. Sub Functions in main.c Source File 1.11.2. Functions in rules.c Source File 1.11.3. Custom Peripheral Access Macros in macros.c Source File
1. Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit

1.6. Generating Programming File

To compile the HDL and generate the programming file (.sof), follow these steps:

  1. Extract the reference design from jesd204b_nios_ref_design.zip.
  2. Launch the Quartus II software.
  3. On the File menu, click Open Project.
  4. Navigate to your project directory and select the Quartus project archive file (jesd204b_ed.qar). Click Open.
  5. In the Restore Archived Project window, verify that the archive file name is jesd204b_ed.qar and set the destination folder to <project directory>/jesd204b_nios_ref_design/jesd204b_ed/. Click OK. The Quartus project is now open in the Quartus window.
  6. In the top level HDL file, <project directory>/jesd204b_nios_ref_design/jesd204b_ed/jesd204b_ed.sv, set the project parameter settings according to your configuration. Ensure that the settings match the JESD204B parameter settings in QSYS. Refer to the Top Level HDL Parameters section for more details on the project parameters
  7. To compile the HDL, navigate to the Processing menu and select Start Compilation.
  8. After compilation is done, you are ready to program the FPGA device with the programming file. Navigate to the Tools menu and click Programmer.
  9. In the Programmer window, click Add File.
  10. In the Select Programming File window, navigate to <project directory>/jesd204b_nios_ref_design/jesd204b_ed/output_files/jesd204b_ed.sof and click Open.
  11. Verify that all the hardware setup options are set correctly to your system configurations.
  12. Click Start to download the file into the Arria 10 FPGA device on the development board.

Alternatively, if you want to use the pre-generated golden programming file, skip the Quartus compilation in step 6 and 7. In step 10, select <project directory>/jesd204b_nios_ref_design/jesd204b_ed/output_files/jesd204b_ed_golden.sof and proceed accordingly.

After programming the Arria 10 FPGA device on the development board, the system needs to be initialized via software before the link can be fully active. Follow the steps in the Setting Up the Software Command Line Environment section to complete the link initialization process.

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