Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Creating a Partial Reconfiguration Design 3. Partial Reconfiguration Solutions IP User Guide A. Partial Reconfiguration M20K Protection Methodology for Intel Agilex 7 Devices B. Intel® Quartus® Prime Pro Edition User Guides
2. Creating a Partial Reconfiguration Design x
2.1. What's New In This Version 2.2. Partial Reconfiguration Terminology 2.3. Partial Reconfiguration Process Sequence 2.4. Internal Host Partial Reconfiguration 2.5. External Host Partial Reconfiguration 2.6. Partial Reconfiguration Design Flow 2.7. Partial Reconfiguration Design Considerations 2.8. Hierarchical Partial Reconfiguration 2.9. Partial Reconfiguration Design Timing Analysis 2.10. Partial Reconfiguration Design Simulation 2.11. Partial Reconfiguration Design Debugging 2.12. Partial Reconfiguration Security ( Intel® Stratix® 10 Designs and Intel Agilex® 7 Designs) 2.13. PR Bitstream Compression and Encryption ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs) 2.14. Avoiding PR Programming Errors 2.15. Exporting a Version-Compatible Compilation Database for PR Designs 2.16. Creating a Partial Reconfiguration Design Revision History
2.6. Partial Reconfiguration Design Flow x
2.6.1. Step 1: Identify Partial Reconfiguration Resources 2.6.2. Step 2: Create Design Partitions 2.6.3. Step 3: Floorplan the Design 2.6.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP 2.6.5. Step 5: Define Personas 2.6.6. Step 6: Create Revisions for Personas 2.6.7. Step 7: Compile the Base Revision and Export the Static Region 2.6.8. Step 8: Setup PR Implementation Revisions 2.6.9. Step 9: Program the FPGA Device
2.6.3. Step 3: Floorplan the Design x
2.6.3.1. Applying Floorplan Constraints Incrementally
2.6.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP x
2.6.4.1. Adding the Partial Reconfiguration Controller Intel FPGA IP 2.6.4.2. Adding the Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP
2.6.9. Step 9: Program the FPGA Device x
2.6.9.1. Generating PR Bitstream Files 2.6.9.2. Generating PR Bitstream Files 2.6.9.3. Partial Reconfiguration Bitstream Compatibility Checking 2.6.9.4. Raw Binary Programming File Byte Sequence Transmission Examples 2.6.9.5. Generating a Merged .pmsf File from Multiple .pmsf Files ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)
2.7. Partial Reconfiguration Design Considerations x
2.7.1. Partial Reconfiguration Design Guidelines 2.7.2. PR Design Timing Closure Best Practices 2.7.3. PR File Management 2.7.4. Evaluating PR Region Initial Conditions 2.7.5. Creating Wrapper Logic for PR Regions 2.7.6. Creating Freeze Logic for PR Regions 2.7.7. Resetting the PR Region Registers 2.7.8. Promoting Global Signals in a PR Region 2.7.9. Planning Clocks and other Global Routing 2.7.10. Implementing Clock Enable for On-Chip Memories
2.7.3. PR File Management x
2.7.3.1. Method 1 (Preferred): Specify Unique Entity and File Names for Each Persona 2.7.3.2. Method 2: Set QSF Assignment for a Parameterized PR Persona
2.7.8. Promoting Global Signals in a PR Region x
2.7.8.1. Viewing Row Clock Region Boundaries
2.7.10. Implementing Clock Enable for On-Chip Memories x
2.7.10.1. Clock Gating
2.8. Hierarchical Partial Reconfiguration x
2.8.1. Using Parent QDB Files from Different Compiles
2.9. Partial Reconfiguration Design Timing Analysis x
2.9.1. Running Timing Analysis on Aggregate Revisions
2.10. Partial Reconfiguration Design Simulation x
2.10.1. Partial Reconfiguration Simulation Flow 2.10.2. Simulating PR Persona Replacement
2.10.2. Simulating PR Persona Replacement x
2.10.2.1. altera_pr_persona_if Module 2.10.2.2. altera_pr_wrapper_mux_out Module 2.10.2.3. altera_pr_wrapper_mux_in Module
2.11. Partial Reconfiguration Design Debugging x
2.11.1. Debugging PR Designs with the Signal Tap Logic Analyzer 2.11.2. Instantiating the Intel Configuration Reset Release Endpoint to Debug Logic IP
2.12. Partial Reconfiguration Security ( Intel® Stratix® 10 Designs and Intel Agilex® 7 Designs) x
2.12.1. PR Bitstream Security Validation ( Intel® Stratix® 10 Designs) 2.12.2. PR Bitstream Authentication ( Intel® Stratix® 10 Designs) 2.12.3. PR Bitstream Encryption ( Intel® Stratix® 10 Designs)
2.13. PR Bitstream Compression and Encryption ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs) x
2.13.1. Generating an Encrypted PR Bitstream ( Intel® Arria® 10 or Intel® Cyclone® 10 GX Designs) 2.13.2. Clock-to-Data Ratio for Bitstream Encryption and Compression ( Intel® Arria® 10 or Intel® Cyclone® 10 GX Designs) 2.13.3. Data Compression Comparison
2.15. Exporting a Version-Compatible Compilation Database for PR Designs x
2.15.1. Version-Compatible Database Flow for PR Designs 2.15.2. Generating a Version-Compatible Compilation Database for PR Designs
3. Partial Reconfiguration Solutions IP User Guide x
3.1. Internal and External PR Host Configurations 3.2. Partial Reconfiguration Controller Intel FPGA IP 3.3. Partial Reconfiguration Controller Intel Arria® 10/Cyclone® 10 FPGA IP 3.4. Partial Reconfiguration External Configuration Controller Intel FPGA IP 3.5. Partial Reconfiguration Region Controller Intel® FPGA IP 3.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP 3.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP 3.8. Generating and Simulating Intel® FPGA IP 3.9. Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration Archive 3.10. Partial Reconfiguration Solutions IP User Guide Revision History
3.2. Partial Reconfiguration Controller Intel FPGA IP x
3.2.1. Memory Map 3.2.2. Parameters 3.2.3. Ports 3.2.4. Timing Specifications 3.2.5. PR Error Recovery 3.2.6. Secure Device Manager Firmware Error Reporting
3.2.5. PR Error Recovery x
3.2.5.1. PR Error Recovery Timing Specifications
3.2.6. Secure Device Manager Firmware Error Reporting x
3.2.6.1. SDM Firmware Error Reporting Timing Specification
3.3. Partial Reconfiguration Controller Intel Arria® 10/Cyclone® 10 FPGA IP x
3.3.1. Agent Interface 3.3.2. Reconfiguration Sequence 3.3.3. Interrupt Interface 3.3.4. Parameters 3.3.5. Ports 3.3.6. Timing Specifications 3.3.7. PR Control Block and CRC Block Verilog HDL Manual Instantiation 3.3.8. PR Control Block and CRC Block VHDL Manual Instantiation 3.3.9. PR Control Block Signals 3.3.10. Configuring an External Host for Intel® Arria® 10 or Intel® Cyclone® 10 GX Designs
3.3.4. Parameters x
3.3.4.1. Error Detection CRC Requirements
3.3.8. PR Control Block and CRC Block VHDL Manual Instantiation x
3.3.8.1. PR Control Block and CRC Block VHDL Component Declaration
3.3.9. PR Control Block Signals x
3.3.9.1. PR Control Block Signal Timing Diagrams
3.4. Partial Reconfiguration External Configuration Controller Intel FPGA IP x
3.4.1. Parameters 3.4.2. Ports 3.4.3. Partial Reconfiguration External Controller Intel FPGA IP Timing Specifications 3.4.4. Configuring an External Host for Intel® Stratix® 10 or Intel Agilex® 7 Designs
3.5. Partial Reconfiguration Region Controller Intel® FPGA IP x
3.5.1. Registers 3.5.2. Parameters 3.5.3. Ports
3.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP x
3.6.1. Parameters 3.6.2. Interface Ports
3.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP x
3.7.1. Parameters 3.7.2. Ports
3.8. Generating and Simulating Intel® FPGA IP x
3.8.1. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 3.8.2. Running the Freeze Bridge Update script 3.8.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 3.8.4. Intel® Arria® 10 and Intel® Cyclone® 10 GX PR Control Block Simulation Model 3.8.5. Generating the PR Persona Simulation Model 3.8.6. Secure Device Manager Partial Reconfiguration Simulation Model
3.8.6. Secure Device Manager Partial Reconfiguration Simulation Model x
3.8.6.1. Monitoring the SDM 3.8.6.2. Simulating Unknown Outputs and Persona Activation 3.8.6.3. Simulation RBF Required Word Sequence
A. Partial Reconfiguration M20K Protection Methodology for Intel Agilex 7 Devices x
A.1. Protect M20Ks from Spurious Clock Signals during PR Operation A.2. Partial Reconfiguration M20K Protection Methodology for Intel Agilex 7 Devices Revision History
A.1. Protect M20Ks from Spurious Clock Signals during PR Operation x
A.1.1. Use Case 1: Partial Reconfiguration with the PR Region Controller IP A.1.2. Use Case 2: PR Without the PR Region Controller IP A.1.3. Use Case 3: Hierarchical Partial Reconfiguration A.1.4. Use Case 4: Static Update Partial Reconfiguration
A.1.1. Use Case 1: Partial Reconfiguration with the PR Region Controller IP x
A.1.1.1. RTL Changes for Use Case 1 A.1.1.2. Compilation for Use Case 1 A.1.1.3. Operation in Hardware for Use Case 1
A.1.1.1. RTL Changes for Use Case 1 x
A.1.1.1.1. PR Region Controller CSR Bits for the m20k_ce_ctl Signal
A.1.3. Use Case 3: Hierarchical Partial Reconfiguration x
A.1.3.1. Adding HPR Partitions in a Subsequent Implementation Compile
1. Answers to Top FAQs
2. Creating a Partial Reconfiguration Design
3. Partial Reconfiguration Solutions IP User Guide
A. Partial Reconfiguration M20K Protection Methodology for Intel Agilex 7 Devices
B. Intel® Quartus® Prime Pro Edition User Guides

2.6.3.1. Applying Floorplan Constraints Incrementally

PR implementation requires additional constraints that identify the reconfigurable partitions of the design and device. These constraints significantly impact the Compiler's timing closure ability. You can avoid and more easily correct timing closure issues by incrementally implementing each constraint, running the Compiler, then verifying timing closure.
Note: PR designs require a more constrained floorplan, compared to a flat design. The overall density and performance of a PR design may be lower than an equivalent flat design.
The following steps describe incrementally developing the requirements for your PR design:
  1. Implement the base revision using the most complex persona for each PR partition. This initial implementation must include the complete design with all periphery constraints, and top-level .sdc timing constraints. Do not include any Logic Lock region constraints for the PR regions with this implementation.
  2. Create partitions by setting the region Type option to Default in the Design Partitions Window, for all the PR partitions.
  3. Register the boundaries of each partition to ensure adequate timing margin.
  4. Verify successful timing closure using the Timing Analyzer.
  5. Ensure that all the desired signals are driven on global networks. Disable the Auto Global Clock option in the Fitter (Assignments > Settings > Compiler Settings > Advanced Settings (Fitter)), to avoid promoting non-global signals.
  6. Create Logic Lock core-only placement regions for each of the partitions.
  7. Recompile the base revision with the Logic Lock constraints, and then verify timing closure.
  8. Enable the Reserved option for each Logic Lock region to ensure the exclusive placement of the PR partitions within the placement regions. Enabling the Reserved option avoids placing the static region logic in the placement region of the PR partition.
  9. Recompile the base revision with the Reserved constraint, and then verify timing closure.
  10. In the Design Partitions Window, specify the Type for each of the PR partitions as Reconfigurable. This assignment ensures that the Compiler adds wire LUTs for each interface of the PR partition, and performs additional compilation checks for partial reconfiguration.
  11. Recompile the base revision with the Reconfigurable constraint, and then verify timing closure. You can now export the top-level partition for reuse in the PR implementation compilation of the different personas.
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