Visible to Intel only — GUID: nwj1486074812395
Ixiasoft
Visible to Intel only — GUID: nwj1486074812395
Ixiasoft
3.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP
Interface Type | Behavior |
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Source interface in the PR region with packet transfer (old or new persona) |
|
Source interface in the PR region without packet transfer (old or new persona) | When the freeze signal is high, the Freeze Bridge does not send transactions to the static region. The Freeze Bridge remains idle until the bridge leaves the frozen state. |
Source interface in the PR region with max_channel > 1 (old or new persona) | When multiple channels transfer unfinished transactions, the Freeze Bridge tracks the channel values to ensure that all packet transactions from different channels end by asserting the endofpacket bit during the frozen state. |
Source interface in the PR region with ready_latency > 0 (old or new persona) | When the Freeze Bridge drives endofpacket, valid, or channel outputs to the static region, the Freeze Bridge reads the ready_latency value. The ready_latency value defines the actual clock cycle when the sink component is ready for data. |
Interface Type | Behavior |
---|---|
Sink interface in PR region | For transactions that includes packet transfers, when the freeze signal goes high, the Freeze Bridge holds the ready signal high to the static region source until any unfinished transaction completes. For transactions that do not include packet transfers, when the freeze signal goes high, the Freeze Bridge holds the ready signal low during the freeze period. The illegal_request signal asserts high to indicate that the current transaction is an error. Configure the design to stop sending transactions to the PR region after the illegal_request signal is high. |
Sink interface in PR region with ready_latency > 0 | When the Freeze Bridge drives endofpacket, valid, or channel outputs to the PR region, the Freeze Bridge must observe the ready_latency value. The ready_latency value defines the actual clock cycle when the sink component is ready for data. |