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2.1. What's New In This Version
2.2. Partial Reconfiguration Terminology
2.3. Partial Reconfiguration Process Sequence
2.4. Internal Host Partial Reconfiguration
2.5. External Host Partial Reconfiguration
2.6. Partial Reconfiguration Design Flow
2.7. Partial Reconfiguration Design Considerations
2.8. Hierarchical Partial Reconfiguration
2.9. Partial Reconfiguration Design Timing Analysis
2.10. Partial Reconfiguration Design Simulation
2.11. Partial Reconfiguration Design Debugging
2.12. Partial Reconfiguration Security ( Intel® Stratix® 10 Designs)
2.13. PR Bitstream Compression and Encryption ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)
2.14. Avoiding PR Programming Errors
2.15. Exporting a Version-Compatible Compilation Database for PR Designs
2.16. Creating a Partial Reconfiguration Design Revision History
2.6.1. Step 1: Identify Partial Reconfiguration Resources
2.6.2. Step 2: Create Design Partitions
2.6.3. Step 3: Floorplan the Design
2.6.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP
2.6.5. Step 5: Define Personas
2.6.6. Step 6: Create Revisions for Personas
2.6.7. Step 7: Compile the Base Revision and Export the Static Region
2.6.8. Step 8: Setup PR Implementation Revisions
2.6.9. Step 9: Program the FPGA Device
2.6.9.1. Generating PR Bitstream Files
2.6.9.2. Generating PR Bitstream Files
2.6.9.3. Partial Reconfiguration Bitstream Compatibility Checking
2.6.9.4. Raw Binary Programming File Byte Sequence Transmission Examples
2.6.9.5. Generating a Merged .pmsf File from Multiple .pmsf Files ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)
2.7.1. Partial Reconfiguration Design Guidelines
2.7.2. PR Design Timing Closure Best Practices
2.7.3. PR File Management
2.7.4. Evaluating PR Region Initial Conditions
2.7.5. Creating Wrapper Logic for PR Regions
2.7.6. Creating Freeze Logic for PR Regions
2.7.7. Resetting the PR Region Registers
2.7.8. Promoting Global Signals in a PR Region
2.7.9. Planning Clocks and other Global Routing
2.7.10. Implementing Clock Enable for On-Chip Memories
3.1. Internal and External PR Host Configurations
3.2. Partial Reconfiguration Controller Intel FPGA IP
3.3. Partial Reconfiguration Controller Intel Arria® 10/Cyclone® 10 FPGA IP
3.4. Partial Reconfiguration External Configuration Controller Intel FPGA IP
3.5. Partial Reconfiguration Region Controller Intel® FPGA IP
3.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP
3.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP
3.8. Generating and Simulating Intel® FPGA IP
3.9. Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration Archive
3.10. Partial Reconfiguration Solutions IP User Guide Revision History
3.3.1. Agent Interface
3.3.2. Reconfiguration Sequence
3.3.3. Interrupt Interface
3.3.4. Parameters
3.3.5. Ports
3.3.6. Timing Specifications
3.3.7. PR Control Block and CRC Block Verilog HDL Manual Instantiation
3.3.8. PR Control Block and CRC Block VHDL Manual Instantiation
3.3.9. PR Control Block Signals
3.3.10. Configuring an External Host for Intel® Arria® 10 or Intel® Cyclone® 10 GX Designs
3.8.1. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
3.8.2. Running the Freeze Bridge Update script
3.8.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3.8.4. Intel® Arria® 10 and Intel® Cyclone® 10 GX PR Control Block Simulation Model
3.8.5. Generating the PR Persona Simulation Model
3.8.6. Secure Device Manager Partial Reconfiguration Simulation Model
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2.15.2. Generating a Version-Compatible Compilation Database for PR Designs
Follow these steps to generate a version-compatible compilation database for PR designs:
- Export the entire compiled design from the Intel® Quartus® Prime software version N by clicking Project > Export Design, or by command line:
quartus_cdb <project> -c <base_revision> --export_design --snapshot final \ --file <base_revision>.qdb
- Import the compiled design to the Intel® Quartus® Prime software version M by clicking Project > Import Design, or by command line:
quartus_cdb <project> -c <base_revision_import> --import_design --file \ <base_revision>.qdb
Note: Whenever possible, import the design into a different working directory than the directory that you use to compile the base design. If you must use the same directory for import and for compiling the base design, make a backup copy of your compiled design by archiving that design with qdb/* included, or make a copy of the entire directory and subdirectories elsewhere. You must also remove the old database directory qdb/* and all the bitstream related files (*.sof, *.msf, *.pmsf). - Rerun the finalize stage of the Fitter in the Intel® Quartus® Prime Pro Edition software version M by clicking Processing > Start > Start Fitter (Finalize), or by command line:
quartus_fit <project> -c <base_revision_import> --finalize
- Run the Assembler in the Intel® Quartus® Prime Pro Edition software version M to regenerate the static region bitstream by clicking Processing > Start > Start Assembler, or by command line:
quartus_asm <project> -c <base_revision_import>
- Export the static region .qdb in the Intel® Quartus® Prime Pro Edition software version M by clicking Project > Export Design Partition, or by command line:
quartus_cdb <project> -c <base_revision_import> --export_block \ root_partition --snapshot final --file --include_sdc_entity_in_partition static.qdb
Note: When exporting the base revision and the static partition, you must include any .sdc files that apply to the partition, by using the include_sdc_entity_in_partition option. - Compile each implementation revision in the Intel® Quartus® Prime Pro Edition software version M, using the static revision .qdb that you exported in the previous step.
quartus_sh –flow compile <project> –c <impl_rev>