Visible to Intel only — GUID: smq1491340852383
Ixiasoft
Visible to Intel only — GUID: smq1491340852383
Ixiasoft
3.3.5. Ports
Port Name | Width | Direction | Function |
---|---|---|---|
nreset |
1 | Input |
Asynchronous reset for the PR Controller IP core. Resetting the PR Controller IP core during a partial reconfiguration operation initiates the withdrawal sequence. |
clk |
1 | Input |
User input clock to the PR Controller IP core. The IP core has a maximum clock frequency of 100MHz. The IP core ignores this signal during JTAG debug operations. |
Port Name | Width | Direction | Function |
---|---|---|---|
freeze |
1 | Output |
Active high signal that freezes the PR interface signals of any region undergoing partial reconfiguration. De-assertion of this signal indicates the end of PR operation. Use the Partial Reconfiguration Region Controller IP for this operation rather than the Partial Reconfiguration Controller IP freeze signal. |
Port Name | Width | Direction | Function |
---|---|---|---|
pr_start |
1 | Input |
A 0 to 1 transition on this port initiates a PR event. You must assert this signal high for a minimum of one clock cycle, and de-assert the signal low prior to the end of the PR operation. This operation ensures the PR Controller IP core is ready to accept the next pr_start trigger event when the freeze signal is low. The PR Controller IP core ignores this signal during JTAG debug operations. |
data[] |
1, 8, 16, or 32 | Input |
Selectable input PR data bus width, either x1, x8, x16, or x32. Once a PR event triggers, the PR event is synchronous with the rising edge of the clk signal, whenever the data_valid signal is high, and the data_ready signal is high. The PR Controller IP core ignores this signal during JTAG debug operations. |
data_valid |
1 | Input |
A 0 to 1 transition on this port indicates the data[] port contains valid data. The PR Controller IP core ignores this signal during JTAG debug operations. |
data_ready |
1 | Output |
A 0 to 1 transition on this port indicates the PR Controller IP core is ready to read the valid data on the data[] port, whenever the data_valid signal asserts high. The data sender must stop sending valid data if this port is low. This signal deasserts low during JTAG debug operations. |
status[2:0] |
1 | Output |
A 3-bit output that indicates the status of PR events. When the IP detects an error (PR_ERROR, CRC_ERROR, or incompatible bitstream error), this signal latches high. This signal only resets at the beginning of the next PR event, when pr_start is high, and freeze is low. For example: 3’b000 – power-up or nreset asserts 3’b001 – PR_ERROR triggers 3’b010 – CRC_ERROR triggers 3’b011 – Incompatible bitstream error detection 3’b100 – PR operation in progress 3’b101 – PR operation passes 3'b110 – Reserved bit 3'b111 – Reserved bit |
Port Name | Width | Direction | Function |
---|---|---|---|
avmm_slave_address |
4 | Input |
Avalon® memory-mapped address bus. The address bus is in the unit of Word addressing. The PR Controller IP core ignores this signal during JTAG debug operations. |
avmm_slave_read | 1 | Input |
Avalon® memory-mapped read control. The PR Controller IP core ignores this signal during JTAG debug operations. |
avmm_slave_readdata | 32 | Output |
Avalon® memory-mapped read data bus. The PR Controller IP core ignores this signal during JTAG debug operations. |
avmm_slave_write | 1 | Input |
Avalon® memory-mapped write control. The PR Controller IP core ignores this signal during JTAG debug operations. |
avmm_slave_writedata | 32 | Input |
Avalon® memory-mapped write data bus. The PR Controller IP core ignores this signal during JTAG debug operations. |
avmm_slave_waitrequest | 1 | Output |
Indicates that the IP is busy. Also indicates that the IP core is unable to respond to a read or write request. The IP core pulls this signal high during JTAG debug operations. |
Port Name | Width | Direction | Function |
---|---|---|---|
irq |
1 | Output |
The interrupt signal. |
Port Name | Width | Direction | Function |
---|---|---|---|
crc_error_pin |
1 | Input |
Available when you use the PR Controller IP core as an External Host. Connect this port to the dedicated CRC_ERROR pin of the FPGA undergoing partial reconfiguration. |
Port Name | Width | Direction | Function |
---|---|---|---|
pr_ready_pin |
1 | Input |
Connect this port to the dedicated PR_READY pin of the FPGA undergoing partial reconfiguration. |
pr_error_pin |
1 | Input |
Connect this port to the dedicated PR_ERROR pin of the FPGA undergoing partial reconfiguration. |
pr_done_pin |
1 | Input |
Connect this port to the dedicated PR_DONE pin of the FPGA undergoing partial reconfiguration. |
pr_request_pin |
1 | Output |
Connect this port to the dedicated PR_REQUEST pin of the FPGA undergoing partial reconfiguration. |
pr_clk_pin |
1 | Output |
Connect this port to the dedicated DCLK of the FPGA undergoing partial reconfiguration. |
pr_data_pin[31..0] |
16|32 | Output |
Connect this port to the dedicated DATA[31..0] pins of the FPGA undergoing partial reconfiguration. |