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2.1. What's New In This Version
2.2. Partial Reconfiguration Terminology
2.3. Partial Reconfiguration Process Sequence
2.4. Internal Host Partial Reconfiguration
2.5. External Host Partial Reconfiguration
2.6. Partial Reconfiguration Design Flow
2.7. Partial Reconfiguration Design Considerations
2.8. Hierarchical Partial Reconfiguration
2.9. Partial Reconfiguration Design Timing Analysis
2.10. Partial Reconfiguration Design Simulation
2.11. Partial Reconfiguration Design Debugging
2.12. Partial Reconfiguration Security ( Intel® Stratix® 10 Designs)
2.13. PR Bitstream Compression and Encryption ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)
2.14. Avoiding PR Programming Errors
2.15. Exporting a Version-Compatible Compilation Database for PR Designs
2.16. Creating a Partial Reconfiguration Design Revision History
2.6.1. Step 1: Identify Partial Reconfiguration Resources
2.6.2. Step 2: Create Design Partitions
2.6.3. Step 3: Floorplan the Design
2.6.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP
2.6.5. Step 5: Define Personas
2.6.6. Step 6: Create Revisions for Personas
2.6.7. Step 7: Compile the Base Revision and Export the Static Region
2.6.8. Step 8: Setup PR Implementation Revisions
2.6.9. Step 9: Program the FPGA Device
2.6.9.1. Generating PR Bitstream Files
2.6.9.2. Generating PR Bitstream Files
2.6.9.3. Partial Reconfiguration Bitstream Compatibility Checking
2.6.9.4. Raw Binary Programming File Byte Sequence Transmission Examples
2.6.9.5. Generating a Merged .pmsf File from Multiple .pmsf Files ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)
2.7.1. Partial Reconfiguration Design Guidelines
2.7.2. PR Design Timing Closure Best Practices
2.7.3. PR File Management
2.7.4. Evaluating PR Region Initial Conditions
2.7.5. Creating Wrapper Logic for PR Regions
2.7.6. Creating Freeze Logic for PR Regions
2.7.7. Resetting the PR Region Registers
2.7.8. Promoting Global Signals in a PR Region
2.7.9. Planning Clocks and other Global Routing
2.7.10. Implementing Clock Enable for On-Chip Memories
3.1. Internal and External PR Host Configurations
3.2. Partial Reconfiguration Controller Intel FPGA IP
3.3. Partial Reconfiguration Controller Intel Arria® 10/Cyclone® 10 FPGA IP
3.4. Partial Reconfiguration External Configuration Controller Intel FPGA IP
3.5. Partial Reconfiguration Region Controller Intel® FPGA IP
3.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP
3.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP
3.8. Generating and Simulating Intel® FPGA IP
3.9. Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration Archive
3.10. Partial Reconfiguration Solutions IP User Guide Revision History
3.3.1. Agent Interface
3.3.2. Reconfiguration Sequence
3.3.3. Interrupt Interface
3.3.4. Parameters
3.3.5. Ports
3.3.6. Timing Specifications
3.3.7. PR Control Block and CRC Block Verilog HDL Manual Instantiation
3.3.8. PR Control Block and CRC Block VHDL Manual Instantiation
3.3.9. PR Control Block Signals
3.3.10. Configuring an External Host for Intel® Arria® 10 or Intel® Cyclone® 10 GX Designs
3.8.1. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
3.8.2. Running the Freeze Bridge Update script
3.8.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3.8.4. Intel® Arria® 10 and Intel® Cyclone® 10 GX PR Control Block Simulation Model
3.8.5. Generating the PR Persona Simulation Model
3.8.6. Secure Device Manager Partial Reconfiguration Simulation Model
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3.3.4.1. Error Detection CRC Requirements
The following describes requirements for enabling the error detection CRC option with various PR configuration method and parameter combinations. Click Assignments > Device > Device & Pin Options > Error Detection CRC > Enable Error Detection Check to enable EDCRC prior to PR bitstream generation.
Note: When using the Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 FPGA IP with a 32-bit Input data width, and with Passive Parallel x1, x8, or x16 configuration, you must turn on the Enable Error Detection Check option, and specify a Divide error detection frequency by value of 2 or 4.
Note: When using the Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 FPGA IP with a 32-bit Input data width and Passive Parallel x32 configuration, PR supports Enable Error Detection Check on or off. If Enable Error Detection Check is on, PR supports all values for Divide error detection frequency by.
Note: When using the Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 FPGA IP with 1, 8, or 16-bit Input data width, and with Passive Parallel x1, x8, x16, or x32 configuration, PR supports Enable Error Detection Check turned on or off. If Enable Error Detection Check is on, PR supports all values for Divide error detection frequency by.
PR IP Input Data Width | Configuration Mode | Enable Error Detection Check | PR Support |
---|---|---|---|
1, 8, 16 | Passive Parallel x1, x8, x16 | Off | Yes |
1, 8, 16 | Passive Parallel x1, x8, x16 | On | Yes, for all Divide error detection frequency by values |
32 | Passive Parallel x1, x8, x16 | Off | No support |
32 | Passive Parallel x1, x8, x16 | On | Yes, for only Divide error detection frequency by value 2 or 4 |
1, 8, 16, 32 | Passive Parallel x32 | Off | Yes |
1, 8, 16, 32 | Passive Parallel x32 | On | Yes, for all Divide error detection frequency by values |