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2.1. What's New In This Version
2.2. Partial Reconfiguration Terminology
2.3. Partial Reconfiguration Process Sequence
2.4. Internal Host Partial Reconfiguration
2.5. External Host Partial Reconfiguration
2.6. Partial Reconfiguration Design Flow
2.7. Partial Reconfiguration Design Considerations
2.8. Hierarchical Partial Reconfiguration
2.9. Partial Reconfiguration Design Timing Analysis
2.10. Partial Reconfiguration Design Simulation
2.11. Partial Reconfiguration Design Debugging
2.12. Partial Reconfiguration Security ( Intel® Stratix® 10 Designs)
2.13. PR Bitstream Compression and Encryption ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)
2.14. Avoiding PR Programming Errors
2.15. Exporting a Version-Compatible Compilation Database for PR Designs
2.16. Creating a Partial Reconfiguration Design Revision History
2.6.1. Step 1: Identify Partial Reconfiguration Resources
2.6.2. Step 2: Create Design Partitions
2.6.3. Step 3: Floorplan the Design
2.6.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP
2.6.5. Step 5: Define Personas
2.6.6. Step 6: Create Revisions for Personas
2.6.7. Step 7: Compile the Base Revision and Export the Static Region
2.6.8. Step 8: Setup PR Implementation Revisions
2.6.9. Step 9: Program the FPGA Device
2.6.9.1. Generating PR Bitstream Files
2.6.9.2. Generating PR Bitstream Files
2.6.9.3. Partial Reconfiguration Bitstream Compatibility Checking
2.6.9.4. Raw Binary Programming File Byte Sequence Transmission Examples
2.6.9.5. Generating a Merged .pmsf File from Multiple .pmsf Files ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)
2.7.1. Partial Reconfiguration Design Guidelines
2.7.2. PR Design Timing Closure Best Practices
2.7.3. PR File Management
2.7.4. Evaluating PR Region Initial Conditions
2.7.5. Creating Wrapper Logic for PR Regions
2.7.6. Creating Freeze Logic for PR Regions
2.7.7. Resetting the PR Region Registers
2.7.8. Promoting Global Signals in a PR Region
2.7.9. Planning Clocks and other Global Routing
2.7.10. Implementing Clock Enable for On-Chip Memories
3.1. Internal and External PR Host Configurations
3.2. Partial Reconfiguration Controller Intel FPGA IP
3.3. Partial Reconfiguration Controller Intel Arria® 10/Cyclone® 10 FPGA IP
3.4. Partial Reconfiguration External Configuration Controller Intel FPGA IP
3.5. Partial Reconfiguration Region Controller Intel® FPGA IP
3.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP
3.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP
3.8. Generating and Simulating Intel® FPGA IP
3.9. Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration Archive
3.10. Partial Reconfiguration Solutions IP User Guide Revision History
3.3.1. Agent Interface
3.3.2. Reconfiguration Sequence
3.3.3. Interrupt Interface
3.3.4. Parameters
3.3.5. Ports
3.3.6. Timing Specifications
3.3.7. PR Control Block and CRC Block Verilog HDL Manual Instantiation
3.3.8. PR Control Block and CRC Block VHDL Manual Instantiation
3.3.9. PR Control Block Signals
3.3.10. Configuring an External Host for Intel® Arria® 10 or Intel® Cyclone® 10 GX Designs
3.8.1. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
3.8.2. Running the Freeze Bridge Update script
3.8.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3.8.4. Intel® Arria® 10 and Intel® Cyclone® 10 GX PR Control Block Simulation Model
3.8.5. Generating the PR Persona Simulation Model
3.8.6. Secure Device Manager Partial Reconfiguration Simulation Model
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3.5.3. Ports
The Partial Reconfiguration Region Controller IP has the following ports.
Port | Width | Direction | Description |
---|---|---|---|
clock_clk | 1 | Input | IP core input clock. |
Reset | |||
reset_reset | 1 | Input | Synchronous reset. |
avl_csr_addr | 2 | Input | Avalon® memory-mapped address bus. The address bus is in word addressing. |
avl_csr_read | 1 | Input | Avalon® memory-mapped read control to CSR block. |
avl_csr_write | 1 | Input | Avalon® memory-mapped write control to CSR. |
avl_csr_writedata | 32 | Input | Avalon® memory-mapped write data bus to CSR. |
avl_csr_readdata | 32 | Output | Avalon® memory-mapped read data bus from CSR. |
interrupt_sender_irq | 1 | output | Trigger by illegal read or illegal write. |
Port | Width | Direction | Description |
---|---|---|---|
pr_handshake_stop_req |
1 | Output | An assertion on this output requests that the PR persona stop executing. |
pr_handshake_stop_ack |
1 | Input | A value of 1 on this input acknowledges that the executing PR persona stops executing and a new persona can replace it. |
pr_handshake_start_req |
1 | Output | An assertion on this output requests that the new PR persona starts executing. |
pr_handshake_start_ack |
1 | Input | A value of 1 on this input acknowledges that the new PR persona starts executing and can stop executing on a pr_handshake_stop_req. |
conduit_control_freeze_req | 1 | Input | Write 1 on this bit to start freezing the PR region interfaces. |
conduit_control_unfreeze_req | 1 | Input | Write 1 on this bit to stop freezing the PR region interfaces. |
conduit_control_freeze_status | 1 | Output | High on this bit indicates that the PR region is successfully goes into freezing state. |
conduit_control_reset | 1 | Input | Write 1 on this bit to reset the PR region. |
conduit_control_unfreeze_status | 1 | Output | High on this bit indicates that the PR region successfully leaves freezing state. |
conduit_control_illegal_req | n | Output | High on this bit indicates illegal data transactions occurring through a Freeze Bridge IP when freeze is active. |
Signal | Width | Direction | Description |
---|---|---|---|
bridge_freeze0_freeze | 1 | Output | This output connects to the freeze input signal of a freeze bridge IP or to control other freeze logic. (Multiple interfaces generate according to the number of freeze interfaces) |
bridge_freeze0_illegal_request | 1 | Input | This input connects to the illegal_request output signal from an instance of the Freeze Bridge IP. |
Figure 70. Partial Reconfiguration Region Controller Interface Ports (Control and Status Register Block Enabled)
Figure 71. Partial Reconfiguration Region Controller Interface Ports (Control and Status Register Block Disabled)