Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 8/26/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Creating a Partial Reconfiguration Design 3. Partial Reconfiguration Solutions IP User Guide A. Intel® Quartus® Prime Pro Edition User Guides
2. Creating a Partial Reconfiguration Design x
2.1. What's New In This Version 2.2. Partial Reconfiguration Terminology 2.3. Partial Reconfiguration Process Sequence 2.4. Internal Host Partial Reconfiguration 2.5. External Host Partial Reconfiguration 2.6. Partial Reconfiguration Design Flow 2.7. Partial Reconfiguration Design Considerations 2.8. Hierarchical Partial Reconfiguration 2.9. Partial Reconfiguration Design Timing Analysis 2.10. Partial Reconfiguration Design Simulation 2.11. Partial Reconfiguration Design Debugging 2.12. Partial Reconfiguration Security ( Intel® Stratix® 10 Designs) 2.13. PR Bitstream Compression and Encryption ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs) 2.14. Avoiding PR Programming Errors 2.15. Exporting a Version-Compatible Compilation Database for PR Designs 2.16. Creating a Partial Reconfiguration Design Revision History
2.6. Partial Reconfiguration Design Flow x
2.6.1. Step 1: Identify Partial Reconfiguration Resources 2.6.2. Step 2: Create Design Partitions 2.6.3. Step 3: Floorplan the Design 2.6.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP 2.6.5. Step 5: Define Personas 2.6.6. Step 6: Create Revisions for Personas 2.6.7. Step 7: Compile the Base Revision and Export the Static Region 2.6.8. Step 8: Setup PR Implementation Revisions 2.6.9. Step 9: Program the FPGA Device
2.6.3. Step 3: Floorplan the Design x
2.6.3.1. Applying Floorplan Constraints Incrementally
2.6.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP x
2.6.4.1. Adding the Partial Reconfiguration Controller Intel FPGA IP 2.6.4.2. Adding the Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP
2.6.9. Step 9: Program the FPGA Device x
2.6.9.1. Generating PR Bitstream Files 2.6.9.2. Generating PR Bitstream Files 2.6.9.3. Partial Reconfiguration Bitstream Compatibility Checking 2.6.9.4. Raw Binary Programming File Byte Sequence Transmission Examples 2.6.9.5. Generating a Merged .pmsf File from Multiple .pmsf Files ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)
2.7. Partial Reconfiguration Design Considerations x
2.7.1. Partial Reconfiguration Design Guidelines 2.7.2. PR Design Timing Closure Best Practices 2.7.3. PR File Management 2.7.4. Evaluating PR Region Initial Conditions 2.7.5. Creating Wrapper Logic for PR Regions 2.7.6. Creating Freeze Logic for PR Regions 2.7.7. Resetting the PR Region Registers 2.7.8. Promoting Global Signals in a PR Region 2.7.9. Planning Clocks and other Global Routing 2.7.10. Implementing Clock Enable for On-Chip Memories
2.7.3. PR File Management x
2.7.3.1. Method 1 (Preferred): Specify Unique Entity and File Names for Each Persona 2.7.3.2. Method 2: Set QSF Assignment for a Parameterized PR Persona
2.7.8. Promoting Global Signals in a PR Region x
2.7.8.1. Viewing Row Clock Region Boundaries
2.7.10. Implementing Clock Enable for On-Chip Memories x
2.7.10.1. Clock Gating
2.8. Hierarchical Partial Reconfiguration x
2.8.1. Using Parent QDB Files from Different Compiles
2.9. Partial Reconfiguration Design Timing Analysis x
2.9.1. Running Timing Analysis on Aggregate Revisions
2.10. Partial Reconfiguration Design Simulation x
2.10.1. Partial Reconfiguration Simulation Flow 2.10.2. Simulating PR Persona Replacement
2.10.2. Simulating PR Persona Replacement x
2.10.2.1. altera_pr_persona_if Module 2.10.2.2. altera_pr_wrapper_mux_out Module 2.10.2.3. altera_pr_wrapper_mux_in Module
2.11. Partial Reconfiguration Design Debugging x
2.11.1. Debugging PR Designs with the Signal Tap Logic Analyzer 2.11.2. Instantiating the Intel Configuration Reset Release Endpoint to Debug Logic IP
2.12. Partial Reconfiguration Security ( Intel® Stratix® 10 Designs) x
2.12.1. PR Bitstream Security Validation ( Intel® Stratix® 10 Designs) 2.12.2. PR Bitstream Authentication ( Intel® Stratix® 10 Designs) 2.12.3. PR Bitstream Encryption ( Intel® Stratix® 10 Designs)
2.13. PR Bitstream Compression and Encryption ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs) x
2.13.1. Generating an Encrypted PR Bitstream ( Intel® Arria® 10 or Intel® Cyclone® 10 GX Designs) 2.13.2. Clock-to-Data Ratio for Bitstream Encryption and Compression ( Intel® Arria® 10 or Intel® Cyclone® 10 GX Designs) 2.13.3. Data Compression Comparison
2.15. Exporting a Version-Compatible Compilation Database for PR Designs x
2.15.1. Version-Compatible Database Flow for PR Designs 2.15.2. Generating a Version-Compatible Compilation Database for PR Designs
3. Partial Reconfiguration Solutions IP User Guide x
3.1. Internal and External PR Host Configurations 3.2. Partial Reconfiguration Controller Intel FPGA IP 3.3. Partial Reconfiguration Controller Intel Arria® 10/Cyclone® 10 FPGA IP 3.4. Partial Reconfiguration External Configuration Controller Intel FPGA IP 3.5. Partial Reconfiguration Region Controller Intel® FPGA IP 3.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP 3.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP 3.8. Generating and Simulating Intel® FPGA IP 3.9. Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration Archive 3.10. Partial Reconfiguration Solutions IP User Guide Revision History
3.2. Partial Reconfiguration Controller Intel FPGA IP x
3.2.1. Memory Map 3.2.2. Parameters 3.2.3. Ports 3.2.4. Timing Specifications 3.2.5. PR Error Recovery 3.2.6. Secure Device Manager Firmware Error Reporting
3.2.5. PR Error Recovery x
3.2.5.1. PR Error Recovery Timing Specifications
3.2.6. Secure Device Manager Firmware Error Reporting x
3.2.6.1. SDM Firmware Error Reporting Timing Specification
3.3. Partial Reconfiguration Controller Intel Arria® 10/Cyclone® 10 FPGA IP x
3.3.1. Agent Interface 3.3.2. Reconfiguration Sequence 3.3.3. Interrupt Interface 3.3.4. Parameters 3.3.5. Ports 3.3.6. Timing Specifications 3.3.7. PR Control Block and CRC Block Verilog HDL Manual Instantiation 3.3.8. PR Control Block and CRC Block VHDL Manual Instantiation 3.3.9. PR Control Block Signals 3.3.10. Configuring an External Host for Intel® Arria® 10 or Intel® Cyclone® 10 GX Designs
3.3.4. Parameters x
3.3.4.1. Error Detection CRC Requirements
3.3.8. PR Control Block and CRC Block VHDL Manual Instantiation x
3.3.8.1. PR Control Block and CRC Block VHDL Component Declaration
3.3.9. PR Control Block Signals x
3.3.9.1. PR Control Block Signal Timing Diagrams
3.4. Partial Reconfiguration External Configuration Controller Intel FPGA IP x
3.4.1. Parameters 3.4.2. Ports 3.4.3. Partial Reconfiguration External Controller Intel FPGA IP Timing Specifications 3.4.4. Configuring an External Host for Intel® Stratix® 10 or Intel® Agilex™ Designs
3.5. Partial Reconfiguration Region Controller Intel® FPGA IP x
3.5.1. Registers 3.5.2. Parameters 3.5.3. Ports
3.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP x
3.6.1. Parameters 3.6.2. Interface Ports
3.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP x
3.7.1. Parameters 3.7.2. Ports
3.8. Generating and Simulating Intel® FPGA IP x
3.8.1. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 3.8.2. Running the Freeze Bridge Update script 3.8.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 3.8.4. Intel® Arria® 10 and Intel® Cyclone® 10 GX PR Control Block Simulation Model 3.8.5. Generating the PR Persona Simulation Model 3.8.6. Secure Device Manager Partial Reconfiguration Simulation Model
3.8.6. Secure Device Manager Partial Reconfiguration Simulation Model x
3.8.6.1. Monitoring the SDM 3.8.6.2. Simulating Unknown Outputs and Persona Activation 3.8.6.3. Simulation RBF Required Word Sequence
1. Answers to Top FAQs
2. Creating a Partial Reconfiguration Design
3. Partial Reconfiguration Solutions IP User Guide
A. Intel® Quartus® Prime Pro Edition User Guides

2.16. Creating a Partial Reconfiguration Design Revision History

Document Version Intel® Quartus® Prime Version Changes
2022.08.05 22.2
  • Updated What's New In This Version topic to note speed grade, compression, and encryption limitation removal. All speed grades support PR. Compression is always enabled for Intel Agilex devices and Intel Stratix 10 devices. Encryption is supported as part of the bitstream security feature for these devices.
  • Added note about avoiding overlapping routing regions to Step 3: Floorplan the Design topic.
  • Removed speed grade limitations from Partial Reconfiguration Design Considerations topic.
  • Added footnote to Partial Reconfiguration Design Guidelines topic clarifying need to sometimes reset data registers.
  • Corrected figure highlight in Viewing Row Clock Region Boundaries topic.
  • Revised statement about need to install specific IP for debugging the PR region in Debugging PR Regions with the Signal Tap Logic Analyzer topic.
  • Revised Implementing Clock Enable for On-Chip Memories with Initialized Contents for requirement to gate appropriately the Clock Enable signal in some cases.
  • Removed note stating no support for PR bitstream encryption and compression for Intel Agilex devices nor Intel Stratix 10 devices. Compression is always enabled by default for Intel Agilex devices and Intel Stratix 10 devices. Encryption is supported as part of the security feature.
2022.01.11 21.4
  • Add Top FAQs navigation to the cover page.
  • Minor wording changes to Partial Reconfiguration Terminology table.
  • Added What's New in this Version topic.
  • Added clarifying notes to image in Viewing Row Clock Region Boundaries topic.
  • Added note about pin assignments deriving from only from the base revision to Step 3: Floorplan the Design and Step 8: Setup Implementation Revisions Viewing Row Clock Region Boundaries topic.
  • Added notes about the relationship between sector coverage and reconfiguration time to Step 3: Floorplan the Design topic.
  • Removed Post Synthesis Export File substep from Step 7: Compile the Base Revision and Export the Static Region topic.
  • Corrected typo and added note to Step 8: Setup PR Implementation Revisions topic.
  • Revised Generating PR Bitstream Files topic to refer to Convert Programming Files dialog box.
  • Corrected steps in Generating a Version-Compatible Compilation Database for PR Designs topic.
2021.10.04 21.3
  • Updated PR Bitstream Security Validation topic to refer to Programming File Generator and revise figure.
  • Updated PR File Management topic for new QSF assignment method.
  • Clarified device support and corrected code example in Generating a Merged .pmsf File from Multiple .pmsf Files topic.
  • Revised Version-Compatible Database Flow for PR Designs topic equation and figure.
  • Updated non-inclusive terms with "host" and "agent" for Avalon Memory Mapped interface references throughout.
2021.08.02 21.2
  • Updated Register States and Programming Model diagram.
  • Updated Avoiding PR Programming Errors topic SEU note.
2021.06.21 21.2
  • Updated Version-Compatible Compilation Database Support table.
2021.05.06 21.1
  • Indicated support for Intel® Agilex™ design PR bitstream generation, and removed PR bitstream generation limitation notes.
  • Revised Partial Reconfiguration Design Debugging topic.
  • Revised Debugging PR Designs with the Signal Tap Logic Analyzer topic.
  • Added new Instantiating the Intel Configuration Reset Release Endpoint to Debug Logic topic.
  • Updated Partial Reconfiguration Security topic for latest information.
  • Updated PR Bitstream Security Validation topic license statement and to remove outdated references.
  • Revised PR Authentication topic use cases.
  • Revised PR Authentication topic use cases.
  • Revised PR Bitstream Encryption topic use case and prerequisites.
2020.12.11 20.3
  • Corrected typo in PMSF file definition in "Using PR Bitstream Security Verification"
2020.09.28 20.3
  • Added note about preserving SDC files to "Step 8: Setup PR Implementation Revisions" topic.
  • Added new "Using Parent QDB Files from Different Compiles" topic.
  • Added "PR Design Timing Closure Best Practices" topic.
  • Replaced references to Avalon-MM and Avalon-ST with Avalon® memory-mapped and Avalon® streaming for legal compliance.
2020.08.07 20.2
  • Added screenshot and details about Synthesis report to "Evaluating PR Region Initial Conditions" topic.
  • Added details about Include entity-bound SDC files option requirements to "Step 7: Compile the Base Revision and Export the Static Region" topic.
  • Removed stated support for "PR Bitstream Security Verification" for Intel® Agilex™ devices. This feature is not yet supported for Intel® Agilex™ devices.
  • Added details about Include entity-bound SDC files option requirements to "Generating a Version-Compatible Compilation Database" for PR Designs topic.
  • Added reference to "EDA Netlist Writer and Gate Level-Netlists" section of the Intel® Quartus® Prime Pro Edition User Guide: Third Party Simulation to the "Partial Reconfiguration Design Simulation" section.
2020.06.22 20.2
  • Added PR simulation support for Intel® Agilex™ designs.
2020.05.11 20.1
  • Revised description of PR bitstream compatibility checking steps for Intel® Cyclone® 10 GX and Intel® Arria® 10 devices.
2020.04.13 20.1
  • Updated requirements in "Partial Reconfiguration Bitstream Compatibility Checking" topic.
  • Added note about time borrowing to "Partial Reconfiguration Design Timing Analysis" topic.
  • Added note indicating HPR designs do not support PR security bitstream verification.
2019.11.18 19.3.0
  • Changed title of "Migrating PR Regions to a Later Software Version" to "Exporting a Version-Compatible Compilation Database for a PR Design," generalized examples, and removed INI requirement.
2019.09.30 19.3.0
  • Added compilation support for Intel® Cyclone® 10 GX and Intel® Agilex™ PR designs.
  • Updated IP name from "Partial Reconfiguration Controller Intel Stratix 10 FPGA IP" to "Partial Reconfiguration Controller Intel FPGA IP" to encompass Intel® Agilex™ designs.
  • Updated wording of "Clock Gating" topic for clarity.
  • Added note to Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP "Parameters" topic about support for enhanced decompression.
2019.06.10 19.1.0
  • Added details about synthesis of PRESERVE_FANOUT_FREE_NODE to "Partial Reconfiguration Design Guidelines."
2019.04.22 19.1.0
  • Indicated support for POF generation support for Intel Cyclone GX devices.
  • Corrected code example in "PR Migration Flow" topic.
2019.04.01 19.1.0
  • Described migration of the static region of a PR design to a later version of the Intel® Quartus® Prime software.
  • Described new "PR Bitstream Security Validation" feature.
  • Described new location of auto export from output_files to project directory.
2018.12.30 18.1.1
  • Described "Partial Reconfiguration Bitstream Compatibility Check" and PR region limitations.
2018.10.24 18.1.0
  • Added "PR File Management" topic.
  • Updated first guideline in "Partial Reconfiguration Design Guidelines."
2018.09.24 18.1.0
  • Described automated .qdb partition export in "Exporting a Design Partition."
  • Added details about required assignments to "Step 6: Create Revisions for Personas."
  • Removed references to placed snapshot. Only synthesized and final snapshots are supported.
  • Corrected description of Entity Re-binding option in Design Partition Settings table.
  • Added command line instructions for creating a revision.
  • Stated PR compilation flow support for Intel® Cyclone® 10 GX devices.
  • Updated Partial Reconfiguration Controller Intel® Arria® 10 FPGA IP name to Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP.
  • Added "Viewing Row Clock Region Boundaries."
  • Added "Planning Clocks and other Global Routing."
2018.07.18 18.0.0
  • Corrected signals in Simulation of PR Persona Switching diagram.
2018.06.18 18.0.0
  • Corrected syntax errors and added note in Running Timing Analysis on Aggregate Revisions.
2018.05.29 18.0.0
  • Added description of "|" that identifies the root partition hierarchy path in Design Partitions Window.
  • Clarified .qsf assignment in Running Timing Analysis on Aggregate Revisions.
2018.05.07 18.0.0
  • Added description of new Partial Reconfiguration External Configuration Controller Intel® Stratix® 10 FPGA IP.
  • Removed descriptions of obsolete synthesis-only revisions and corresponding personas. Replaced with latest simplified flow instructions.
  • Updated names of Partial Reconfiguration Controller Intel® Arria® 10 FPGA IP and Partial Reconfiguration Controller Intel® Stratix® 10 FPGA IP.
  • Added Design Partition Settings topic.
  • Added Evaluating PR Partition Initial Conditions topic.
  • Added Avoiding PR Programming Errors topic.
  • Described qcrypt incompatibility with Enable bitstream compatibility check and workaround.
  • Added as chapter in new Partial Reconfiguration User Guide.
  • Updated command-line syntax in Running Timing Analysis on Aggregate Revisions topic.
  • Removed obsolete HPR flow script information and linked to AN826: Hierarchical Partial Reconfiguration Tutorial for Intel Stratix 10 GX FPGA Development Board
  • Added note about recovery after PR error when using SEU detection in Intel® Stratix® 10 designs.
2017.11.06 17.1.0
  • Added partial reconfiguration support for Intel® Stratix® 10 devices.
  • Added descriptions of Intel® Stratix® 10 Partial Reconfiguration Controller IP, SUPR, HPR, and SDM to terms list.
  • Updated for latest Intel® branding and software user interface.
2017.05.08 17.0.0
  • Added information about Hierarchical Partial Reconfiguration.
  • Added new topic Partial Reconfiguration Simulation and Verification.
  • Added new topic 'Run Timing Analysis on a Design with Multiple PR Partitions'.
  • Updated Freeze Logic for PR Regions.
  • Added new topic Debugging Using Signal Tap Logic Analyzer.
  • Other minor updates.
10.31.2016 16.1.0
  • Initial release.
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