F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 6/20/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Generating Tile Files 1.4. Simulating the Design Example Testbench 1.5. Hardware and Software Requirements 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.8. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Multiple IP Instance Design
1.4. Simulating the Design Example Testbench x
1.4.1. Fast Sim Model for FGT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes

The following steps show the simulation testbench flow for PCS, OTN, and FlexE modes:
  1. Assert global reset (i_rst_n) to reset the F-Tile Ethernet Intel FPGA Hard IP.
  2. Wait until resets acknowledgment. The o_rst_ack_n signal goes low.
  3. Deasserts the global reset.
  4. Wait until o_tx_lanes_stable bit is set to 1, indicating TX path is ready.
  5. Wait until o_rx_pcs_ready bit is set to 1, indicating RX path is ready.
    Note: In non-MAC mode, the packet client sends out idle data in MII/PCS66 format.
  6. Read TX packet data information from 0x00 - 0x34 registers in sequential order.
    • 0x00: Set hw_pc_ctrl[6] = 1'b1 to enable snapshot bit to read the TX packet statistics.
    • 0x020/0x24: TX start of packet counter (LSB/MSB)
    • 0x28/0x2C: TX end of packet counter (LSB/MSB)
    • 0x00: Set hw_pc_ctrl[6] = 1'b0 to disable snapshot bit.
  7. Read RX packet data information from 0x38 - 0x4C registers in sequential order.
    • 0x00: Set hw_pc_ctrl[6] = 1'b1 to enable snapshot bit to read the RX packet statistics.
    • 0x38/0x3C: RX start of packet counter (LSB/MSB)
    • 0x40/0x44: RX end of packet counter (LSB/MSB)
    • 0x48/0x4C: RX error counter (LSB/MSB)
    • 0x00: Set hw_pc_ctrl[6] = 1'b0 to disable snapshot bit.
  8. Compare the counters to ensure 16 packets were sent and received.
  9. Instruct packet client to stop data transmission. Write cfg_start_pkt_gen[0]=1'b1 to stop the packet generator. Clear counters.
  10. Perform Avalon® memory-mapped interface test. Write and read Ethernet IP registers.
    • 0x104: Scratch register
    • 0x108: Ethernet IP soft reset register
    • 0x004: Ethernet IP debug configuration control register
    • 0x008: Ethernet IP enable/clock gating configuration register
  11. Perform Avalon® memory-mapped interface 2 test. Write and read transceiver registers.
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