F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 6/20/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Generating Tile Files 1.4. Simulating the Design Example Testbench 1.5. Hardware and Software Requirements 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.8. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Multiple IP Instance Design
1.4. Simulating the Design Example Testbench x
1.4.1. Fast Sim Model for FGT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.6.20 22.2 6.0.0 Made the following changes:
  • Added clock controller screenshot and updated steps in Compiling and Configuring the Design Example in Hardware.
  • Updated Design Example: Single IP Core Instantiation with Precision Time Protocol:

    - Updated steps in Hardware Design Example.

  • Removed note about i_reconfig_clk clock frequency limitation in Functional Description.
  • Added FGT and FHT macros to simulation run script for AN/LT enabled designs in simulation.
2022.01.30 21.4 4.0.0
  • Added support for the Xcelium* simulator.
  • Updated quick start guide sub-sections:
    • Globally added support for the Agilex I-Series Transceiver-SoC Development Kit.
    • Updated Generating Tile Files.
    • Added new topic: Compiling and Configuring the Design Example in Hardware.
    • Updated steps in Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example.
  • Updated Design Example: Single IP Core Instantiation with Precision Time Protocol:
    • Added note about i_reconfig_clk clock frequency limitation.
    • Revised the sample output in the Simulation section.
    • Added new topic: Hardware Design Example.
  • Updated Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training:
    • Replaced the placement assignments with the colocate assignments.
    • Updated simulation flow.
    • Updated QSF assignments.
2021.10.11 21.3 3.0.0
  • Added pin assignment requirement for AN/LT designs in Generating Tile Files.
  • Updated the list of supported simulators in Simulating the Design Example Testbench.
  • Added new topics:
    • Fast Sim Model
    • Testing the Hardware Design Example
    • Register Maps
    • Simulation Testbench Flow for PCS, OTN, and FlexE Modes
  • Updated register descriptions in Packet Client Registers.
  • Updated PTP-related Registers section. Address offset is specified as a byte address.
  • Added new design examples: Single IP Core Instantiation with Auto-Negotiation and Link Training
2021.07.01 21.2 2.0.0 Initial release.
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