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1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1.1. Generating the Design
1.2. Directory Structure
1.3. Generating Tile Files
1.4. Simulating the Design Example Testbench
1.5. Hardware and Software Requirements
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example
1.8. Register Maps
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4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
This design example describes necessary steps to enable auto-negotiation and link training (AN/LT) in your design example.
When you enable auto-negotiation and link training parameter in the IP and generate a design example, the design example instantiates two separate IPs, F-Tile Ethernet Intel FPGA Hard IP and the F-Tile Auto-Negotiation and Link Training for Ethernet. You must connect required signals at the top level of your testbench.
The following IP parameter settings were used to generate this design example:
Selected IP Parameter Settings | Value |
---|---|
General Options | |
PMA type | FGT |
Ethernet mode | 100GE-4 |
Client interface | MAC segmented |
FEC mode | IEEE 802.3 RS(528,514) (CL91) |
PMA reference frequency | 156.25 MHz |
System PLL frequency | 805.6640625 MHz |
Selected IP Parameter Settings | Value |
---|---|
Mode Selection | |
Enable auto-negotiation on reset | On |
Enable link training on reset | On |
PMA type | FGT |
Ethernet mode | 100GE-4 |
KR or CR mode | KR mode |
Number of ports | 1 |
FEC mode | IEEE 802.3 RS(528,514) |
Status clock frequency | 100 MHz |
For more information about steps of how to generate a design example, refer to the Generating the Design Example.
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