6.1.9. HDCP 1.4 RX Architecture

HDMI Intel® FPGA IP User Guide

Download PDF

ID 683798

Date 12/04/2023

Version

Public

Visible to Intel only — GUID: iby1559235473920

Ixiasoft

View Details

6.1.9. HDCP 1.4 RX Architecture

The HDCP 1.4 receiver block decrypts the protected video and auxiliary data from the connected HDCP 1.4 device. The HDCP 1.4 receiver block has identical structure layers as the HDCP 1.4 transmitter block.

Figure 55. Architecture Block Diagram of HDCP 1.4 RX IP

The HDCP 1.4 RX core is fully autonomous. For HDMI application, the transmitter drives the HDCP 1.4 RX core using the standard DDC interface supporting I²C protocol. You need an I²C slave externally to drive the IP through the HDCP Register Port ( Avalon® memory-mapped interface).

The HDCP specifications requires the HDCP 2.3 RX core to be programmed with the DCP-issued production key – Device Private Keys (Bkeys) and Key Selection Vector (Bksv). The IP retrieves the key from the on-chip memory externally to the core through the HDCP Key Port. The on-chip memory must store the key data in the arrangement shown in the table below.

Table 55. HDCP 1.4 RX Key Port Addressing
Address	Content
6'h28	{16’d0, Bksv[39:0]}
6'h27	Bkeys39[55:0]
6'h26	Bkeys38[55:0]
...	...
6'h01	Bkeys01[55:0]
6'h00	Bkeys00[55:0]

The Video Stream and Auxiliary Layer receives audio and video content over its Video and Aux Data Input Port, and performs the decryption operation. The Video Stream and Auxiliary Layer detects the Encryption Status Signaling (ESS) provided by the HDMI IP to determine when to decrypt frames.

To implement the HDCP 1.4 RX core as a repeater upstream interface, the IP must propagate certain information such as KSV list and Bstatus to the upstream transmitter and to be used for SHA-1 hash digest. The repeater downstream interface (TX) must provide this information using the Repeater Message Port ( Avalon® memory-mapped interface). You can use the same clock source to drive the clocking for the HDCP Register Port and Repeater Message Port.

The RX registers mapping defined in the following table is equivalent to the address space for HDCP 1.4 receiver defined in the HDCP specification.

Table 56. HDCP 1.4 RX Registers Mapping
Address	Register	R/W	Reset	Bit	Bit Name	Description
0x00	`BKSV0`	RO	-	7:0	—	Bit [7:0] of HDCP Receiver KSV.
0x01	`BKSV1`		-	7:0		Bit [15:8] of HDCP Receiver KSV.
0x02	`BKSV2`		-	7:0		Bit [23:16] of HDCP Receiver KSV.
0x03	`BKSV3`		-	7:0		Bit [31:24] of HDCP Receiver KSV.
0x04	`BKSV4`		-	7:0		Bit [39:32] of HDCP Receiver KSV.
0x05-0x07	Rsvd	RO	0x00	7:0	—	Reserved. All bytes read as 0x00.
0x08	`RI_PRIME0`	RO	0x00	7:0	—	Link verification response. Bit [7:0] of Ri’.
0x09	`RI_PRIME1`	RO	0x00	7:0	—	Link verification response. Bit [15:8] of Ri’.
0x0A	`PJ_PRIME`	RO	0x00	7:0	—	Reserved. All bytes read as 0x00.
0x0B – 0x0F	Rsvd	RO	0x00	7:0	—	Reserved. All bytes read as 0x00.
0x10	`AKSV0`	WO	0x00	7:0	—	Bit [7:0] of HDCP Transmitter KSV.
0x11	`AKSV1`		0x00	7:0		Bit [15:8] of HDCP Transmitter KSV.
0x12	`AKSV2`		0x00	7:0		Bit [23:16] of HDCP Transmitter KSV.
0x13	`AKSV3`		0x00	7:0		Bit [31:24] of HDCP Transmitter KSV.
0x14	`AKSV4`		0x00	7:0		Bit [39:32] of HDCP Transmitter KSV.
0x15	`AINFO`	WO	0x00	7:0	—	Reserved.
0x16 – 0x17	Rsvd	RO	0x00	7:0	—	Reserved. All bytes read as 0x00.
0x18	`AN0`	WO	0x00	7:0	—	Bit [7:0] of HDCP Session Random Number An.
0x19	`AN1`		0x00	7:0		Bit [15:8] of HDCP Session Random Number An.
0x1A	`AN2`		0x00	7:0		Bit [23:16] of HDCP Session Random Number An.
0x1B	`AN3`		0x00	7:0		Bit [31:24] of HDCP Session Random Number An.
0x1C	`AN4`		0x00	7:0		Bit [39:32] of HDCP Session Random Number An.
0x1D	`AN5`		0x00	7:0		Bit [47:40] of HDCP Session Random Number An.
0x1E	`AN6`		0x00	7:0		Bit [55:48] of HDCP Session Random Number An.
0x1F	`AN7`		0x00	7:0		Bit [63:56] of HDCP Session Random Number An.
0x20	`V_PRIME_H0_0`	RO	0x00	7:0	—	H0 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H0 value.
0x21	`V_PRIME_H0_1`		0x00	7:0		Bit [15:8] of H0 value.
0x22	`V_PRIME_H0_2`		0x00	7:0		Bit [23:16] of H0 value.
0x23	`V_PRIME_H0_3`		0x00	7:0		Bit [31:24] of H0 value.
0x24	`V_PRIME_H1_0`	RO	0x00	7:0	—	H1 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H1 value.
0x25	`V_PRIME_H1_1`		0x00	7:0		Bit [15:8] of H1 value.
0x26	`V_PRIME_H1_2`		0x00	7:0		Bit [23:16] of H1 value.
0x27	`V_PRIME_H1_3`		0x00	7:0		Bit [31:24] of H1 value.
0x28	`V_PRIME_H2_0`	RO	0x00	7:0	`-`	H2 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H2 value.
0x29	`V_PRIME_H2_1`		0x00	7:0		Bit [15:8] of H2 value.
0x2A	`V_PRIME_H2_2`		0x00	7:0		Bit [23:16] of H2 value.
0x2B	`V_PRIME_H2_3`		0x00	7:0		Bit [31:24] of H2 value.
0x2C	`V_PRIME_H3_0`	RO	0x00	7:0	—	H3 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H3 value.
0x2D	`V_PRIME_H3_1`		0x00	7:0		Bit [15:8] of H3 value.
0x2E	`V_PRIME_H3_2`		0x00	7:0		Bit [23:16] of H3 value.
0x2F	`V_PRIME_H3_3`		0x00	7:0		Bit [31:24] of H3 value.
0x30	`V_PRIME_H4_0`	RO	0x00	7:0	—	H4 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H4 value.
0x31	`V_PRIME_H4_1`		0x00	7:0		Bit [15:8] of H4 value.
0x32	`V_PRIME_H4_2`		0x00	7:0		Bit [23:16] of H4 value.
0x33	`V_PRIME_H4_3`		0x00	7:0		Bit [31:24] of H4 value.
0x34 – 0x3F	Rsvd	RO	0x00	7:0	—	Reserved. All bytes read as 00.
0x40	`BCAPS`	RO	0x00	7	`HDMI_RESERVED`	0 = Receiver not capable of supporting HDMI 1 = Receiver capable of supporting HDMI
				6	`REPEATER`	HDCP repeater capability. 0 = Receiver is not a repeater. 1 = Receiver is a repeater.
				5	`READY`	KSV FIFO ready. When set to 1, the receiver has built the list of attached KSVs and computed the verification value V’. This value is always 0 during the computation of V’.
				4	`FAST`	This bit reads as 0.
				3:2	`Reserved`	These bits read as 0.
				1	`FEATURES_1_1`	Reserved. This bit reads as 0.
				0	`FAST_` `REAUTHENTICATION`	This bit reads as 1.
0x41	`BSTATUS0`	RO	0x00	7	`MAX_DEVS_` `EXCEEDED`	Topology error indicator. When set to 1, more than 127 downstream devices, or the capacity of the KSV FIFO, are attached.
0x41	`BSTATUS0`		0x00	6:0	`DEVICE_COUNT`	Total number of attached downstream devices. Always 0 for HDCP Receivers. This count does not include the HDCP Repeater itself, but only downstream devices downstream from the HDCP Repeater.
0x42	`BSTATUS1`		0x00	7:6	`Rsvd`	These bits read as 0.
				5	`HDMI_RESERVED_2`	Reserved for future possible HDMI use.
				4	`HDMI_MODE`	HDMI mode. When set to 1, the HDCP Receiver has transitioned from DVI mode to HDMI mode.
				3	`MAX_CASCADE_EXCEEDED`	Topology error indicator. When set to 1, more than 7 levels of video repeater have been cascaded together.
				2:0	`DEPTH`	3-bit repeater cascade depth. This value gives the number of attached levels through the connection topology.
0x43	`KSV_FIFO`	RO	0x00	7:0	`-`	Key selection vector FIFO. Used to pull downstream KSVs from HDCP Repeaters.
0x44 – 0xBF	Rsvd	RO	0x00	7:0	`-`	Reserved. All bytes read as 0x00.
0xC0 – 0x100	`DBG`	RW	0x00	7:0	`-`	Implementation-specific debug registers.

Table 57. HDCP 1.4 RX Repeater Registers Mapping
Address	Register	R/W	Reset	Bit	Bit Name	Description
0x00	`RPT_KSV_LIST`	WO	0x00000000	31:8	Reserved	Reserved
0x00	`RPT_KSV_LIST`	WO	0x00000000	7:0	`KSV_LIST`	Byte write KSV List in big endian order.
0x01	`RPT_BSTATUS`	RW	0x00000000	31:19	Reserved	Reserved
				18	`REQUEST`	Read-only. Asserted by the core to request for `KSV_LIST` and `BSTATUS.` This usually happens when re-authentication is triggered by the connected upstream. Note that when `REQUEST` is asserted, the `READY` should also be asserted.
				17	`READY`	Read-only. Asserted by the core to indicate `KSV_LIST` and `BSTATUS` are processed. Write `KSV_LIST` and `BSTATUS` after this bit is asserted.
				16	`VALID`	Set to 1 after `KSV_LIST` and `BSTATUS` are written. Self-cleared by the core after `KSV_LIST` and `BSTATUS` are read.
				15:0	`BSTATUS`	[15:12]: Reserved. [11]: `MAX_CASCADE_EXCEEDED` [10:8]: `DEPTH` [7]: `MAX_DEVS_EXCEEDED` [6:0]: `DEVICE_COUNT`
0x02	`RPT_MISC`	RW	–	31:1	Reserved	Reserved.
0x02	`RPT_MISC`	RW	–	0	`REPEATER`	Set to 0 if no downstream is connected or if the connected downstream is not HDCP 1.4-capable. This means the receiver IP core is an end-point receiver rather than a repeater. Set to 1 if the connected downstream is HDCP-capable.

Select Your Language

Using Intel.com Search

Quick Links

Recent Searches

Advanced Search

Only search in

HDMI Intel® FPGA IP User Guide

6.1.9. HDCP 1.4 RX Architecture