HDMI Intel® FPGA IP User Guide

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ID 683798
Date 11/12/2021
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Quick Reference 2. HDMI Overview 3. HDMI Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI Source 6. HDMI Sink 7. HDMI Parameters 8. HDMI Simulation Example 9. HDMI Intel® FPGA IP User Guide Archives 10. Document Revision History for the HDMI Intel® FPGA IP User Guide
2. HDMI Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel Arria 10, Intel Cyclone 10 GX, and Intel Stratix 10 Devices 4.2. HDCP Over HDMI Design Example for Intel® Arria® 10 and Intel® Stratix® 10 Devices 4.3. HDMI Hardware Design Examples for Arria V and Stratix V Devices
4.3. HDMI Hardware Design Examples for Arria V and Stratix V Devices x
4.3.1. HDMI Hardware Design Components 4.3.2. HDMI Hardware Design Requirements 4.3.3. Design Walkthrough
4.3.1. HDMI Hardware Design Components x
4.3.1.1. Transceiver Native PHY (RX) 4.3.1.2. PLL Intel FPGA IP Cores 4.3.1.3. PLL Reconfig Intel FPGA IP Core 4.3.1.4. Multirate Reconfig Controller (RX) 4.3.1.5. Oversampler (RX) 4.3.1.6. DCFIFO 4.3.1.7. Sink Display Data Channel (DDC) & Status and Control Data Channel (SCDC) 4.3.1.8. Transceiver Reconfiguration Controller 4.3.1.9. VIP Bypass and Audio, Auxiliary and InfoFrame Buffers 4.3.1.10. Transceiver Native PHY (TX) 4.3.1.11. Transceiver PHY Reset Controller 4.3.1.12. Oversampler (TX) 4.3.1.13. Clock Enable Generator 4.3.1.14. Platform Designer System
4.3.1.14. Platform Designer System x
4.3.1.14.1. VIP Passthrough for HDMI Video Stream 4.3.1.14.2. Source SCDC Controller 4.3.1.14.3. Source Reconfiguration Controller
4.3.3. Design Walkthrough x
4.3.3.1. Set Up the Hardware 4.3.3.2. Copy the Design Files 4.3.3.3. Build and Compile the Design 4.3.3.4. View the Results
4.3.3.4. View the Results x
4.3.3.4.1. Push Buttons, DIP Switches and LED Functions
5. HDMI Source x
5.1. Source Functional Description 5.2. Source Interfaces 5.3. Source Clock Tree 5.4. Link Training Procedure 5.5. FRL Clocking Scheme 5.6. Valid Video Data 5.7. Source Deep Color Implementation When Support FRL = 0 5.8. Source Deep Color Implementation When Support FRL = 1 5.9. Variable Refresh Rate (VRR) and Auto Low Latency Mode (ALLM)
5.1. Source Functional Description x
5.1.1. Source Scrambler, TMDS/TERC4 Encoder 5.1.2. Source Video Resampler 5.1.3. Source Window of Opportunity Generator 5.1.4. Source Auxiliary Packet Encoder 5.1.5. Source Auxiliary Packet Generators 5.1.6. Source Auxiliary Data Path Multiplexers 5.1.7. Source Auxiliary Control Port 5.1.8. Source Audio Encoder 5.1.9. HDCP 1.4 TX Architecture 5.1.10. HDCP 2.3 TX Architecture 5.1.11. FRL Packetizer 5.1.12. FRL Character Block and Super Block Mapping 5.1.13. Reed-Solomon (RS) Forward Error Correction (FEC) Generation and Insertion 5.1.14. FRL Scrambler and Encoder 5.1.15. Source FRL Resampler 5.1.16. TX Oversampler 5.1.17. Clock Enable Generator 5.1.18. I2C Master
5.1.7. Source Auxiliary Control Port x
5.1.7.1. Source General Control Packet (GCP) 5.1.7.2. Source Auxiliary Video Information (AVI) InfoFrame Bit-Fields 5.1.7.3. Source HDMI Vendor Specific InfoFrame (VSI)
5.1.8. Source Audio Encoder x
5.1.8.1. Audio InfoFrame (AI) Bundle Bit-Fields 5.1.8.2. Audio Metadata Bundle Bit-Fields
6. HDMI Sink x
6.1. Sink Functional Description 6.2. Sink Interfaces 6.3. Sink Clock Tree 6.4. Link Training Procedure 6.5. Sink Deep Color Implementation When Support FRL = 0 6.6. Sink Deep Color Implementation When Support FRL = 1
6.1. Sink Functional Description x
6.1.1. Sink Word Alignment and Channel Deskew 6.1.2. Sink Descrambler, TMDS/TERC4 Decoder 6.1.3. Sink Auxiliary Decoder 6.1.4. Sink Auxiliary Packet Capture 6.1.5. Sink Video Resampler 6.1.6. Sink Auxiliary Data Port 6.1.7. Sink Audio Decoder 6.1.8. Status and Control Data Channel (SCDC) Interface 6.1.9. HDCP 1.4 RX Architecture 6.1.10. HDCP 2.3 RX Architecture 6.1.11. FRL Depacketizer 6.1.12. Sink FRL Character Block and Super Block Demapper 6.1.13. Sink FRL Descrambler and Decoder 6.1.14. Sink FRL Resampler 6.1.15. RX Oversampler 6.1.16. I2C Slave 6.1.17. I2C and EDID RAM Blocks 6.1.18. Variable Refresh Rate(VRR) and Auto Low Latency Mode (ALLM)
6.1.6. Sink Auxiliary Data Port x
6.1.6.1. Sink General Control Packet (GCP) 6.1.6.2. Sink Auxiliary Video Information (AVI) InfoFrame Bit-Fields 6.1.6.3. Sink HDMI Vendor Specific InfoFrame (VSI)
6.1.7. Sink Audio Decoder x
6.1.7.1. Audio InfoFrame (AI) Bundle Bit-Fields 6.1.7.2. Audio Metadata Bundle Bit-Fields
7. HDMI Parameters x
7.1. HDMI Source Parameters 7.2. HDMI Sink Parameters
8. HDMI Simulation Example x
8.1. Simulation Walkthrough
1. HDMI Intel® FPGA IP Quick Reference
2. HDMI Overview
3. HDMI Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI Source
6. HDMI Sink
7. HDMI Parameters
8. HDMI Simulation Example
9. HDMI Intel® FPGA IP User Guide Archives
10. Document Revision History for the HDMI Intel® FPGA IP User Guide

4.3.1.1. Transceiver Native PHY (RX)

  • Transceiver Native PHY in Arria V devices
    • To operate the TMDS bit rate up to 3,400 Mbps, configure the Transceiver Native PHY at 20 bits at PCS – PLD interface with the HDMI RX core at 2 symbols per clock. When the PCS – PLD interface width is 20 bits, the minimum link rate is 611 Mbps.
    • To operate the TMDS bit rate up to 6,000 Mbps, configure the Transceiver Native PHY at 40 bits with the HDMI RX core at 4 symbols per clock. When the PCS – PLD interface width is 40 bits, the minimum link rate is 1,000 Mbps.
    • Oversampling is required for TMDS bit rate which is below the minimum link rate.
  • Transceiver Native PHY in Stratix V devices
    • To operate the TMDS bit rate up to 6,000 Mbps, configure the Transceiver Native PHY at 20 bits at PCS – PLD interface with the HDMI RX core at 2 symbols per clock. When the PCS – PLD interface width is 20 bits, the minimum link rate is 611 Mbps.
Table 11.  Arria V and Stratix V Transceiver Native PHY (RX) Configuration Settings (6,000 Mbps)This table shows an example of Arria V and Stratix V Transceiver Native PHY (RX) configuration settings for TMDS bit rate of 6,000 Mbps.
Parameters Settings
Datapath Options
Enable TX datapath Off
Enable RX datapath On
Enable Standard PCS On
Initial PCS datapath selection Standard
Number of data channels 3
Enable simplified data interface On
RX PMA
Data rate 6,000 Mbps
Enable CDR dynamic reconfiguration On
Number of CDR reference clocks 2 4
Selected CDR reference clock 0 4
Selected CDR reference clock frequency 600 MHz
PPM detector threshold 1,000 PPM
Enable rx_pma_clkout port On
Enable rx_is_lockedtodata port On
Enable rx_is_lockedtoref port On
Enable rx_set_locktodata and rx_set_locktoref ports On
Standard PCS
Standard PCS protocol Basic
Standard PCS/PMA interface width
  • 10 (for 1 symbol per clock)
  • 20 (for 2 and 4 symbols per clock)
Enable RX byte deserializer
  • Off (for 1 and 2 symbols per clock)
  • On (for 4 symbols per clock)
Table 12.  Arria V and Stratix V Transceiver Native PHY (RX) Common Interface PortsThis table describes the Arria V and Stratix V Transceiver Native PHY (RX) common interface ports.
Signals Direction Description
Clocks
rx_cdr_refclk[1:0] Input

Input reference clock for the RX CDR circuitry.

  • To support arbitrary wide data rate range from 250 Mbps to 6,000 Mbps, you need a generic core PLL to obtain a higher clock frequency from the TMDS clock. You need a higher clock frequency to create oversampled stream for data rates below the minimum transceiver data rate—for example, 611 Mbps or 1,000 Mbps).
  • If the TMDS clock pin is routed to the transceiver dedicated reference clock pin, you only need to create one transceiver reference clock input. You can use the TMDS clock as reference clock for a generic core PLL to drive the transceiver.
  • If you use Bitec HDMI HSMC 2.0 daughter card, the TMDS clock pin is routed to the transceiver serial data pin. In this case, to use the TMDS clock as a reference clock for a generic core PLL, the clock must also drive the transceiver dedicated reference clock. Connect bit 0 to the generic core PLL output and bit 1 to the TMDS clock and set the selected CDR reference clock at 0.
rx_std_clkout[2:0] Output

RX parallel clock output.

  • The CDR circuitry recovers the RX parallel clock from the RX data stream when the CDR is configured at lock-to-data mode.
  • The RX parallel clock is a mirror of the CDR reference clock when the CDR is configured at lock-to-reference mode.
rx_std_coreclkin[2:0] Input

RX parallel clock that drives the read side of the RX phase compensation FIFO.

Connect to rx_std_clkout ports.

rx_pma_clkout[2:0] Output

RX parallel clock (recovered clock) output from PMA.

Leave unconnected.
Resets
rx_analogreset[2:0] Input

Active-high, edge-sensitive, asynchronous reset signal.

When asserted, resets the RX CDR circuit, deserializer.

Connect to Transceiver PHY Reset Controller IP core.
rx_digitalreset[2:0] Input

Active-high, edge-sensitive, asynchronous reset signal.

When asserted, resets the digital component of the RX data path.

Connect to the Transceiver PHY Reset Controller IP core.
PMA Ports
rx_set_locktoref[2:0] Input

When asserted, programs the RX CDR to lock to reference mode manually. The lock to reference mode enables you to control the reset sequence using rx_set_locktoref and rx_set_locktodata.

The Multirate Reconfiguration Controller (RX) sets this port to 1 if oversampling mode is required. Otherwise, this port is set to 0.

Refer "Transceiver Reset Sequence" in Transceiver Reset Control in Arria V/Stratix V Devices for more information about manual control of the reset sequence.
rx_set_locktodata[2:0] Input Always driven to 0. When rx_set_locktoref is driven to 1, the CDR is configured to lock-to-reference mode. Otherwise, the CDR is configured to lock-to-data mode.
rx_is_lockedtoref[2:0] Output When asserted, the CDR is locked to the incoming reference clock. Connect this port to rx_is_lockedtodata port of the Transceiver PHY Reset Controller IP core when rx_set_locktoref is 1.
rx_is_lockedtodata[2:0] Output When asserted, the CDR is locked to the incoming data. Connect this port to rx_is_lockedtodata port of Transceiver PHY Reset Controller IP core when rx_set_locktoref is 0.
rx_serial_data[2:0] Input RX differential serial input data.
PCS Ports
unused_rx_parallel_data Output Leave unconnected.
rx_parallel_data[S*3*10-1:0] Output PCS RX parallel data.
Note: S=Symbols per clock.
Calibration Status Port
rx_cal_busy[2:0] Output When asserted, indicates that the initial RX calibration is in progress. This port is also asserted if the reconfiguration controller is reset. Connect to the Transceiver PHY Reset Controller IP core.
Reconfiguration Ports
reconfig_to_xcvr[209:0] Input Reconfiguration signals from the Transceiver Reconfiguration Controller.
reconfig_from_xcvr[137:0] Output Reconfiguration signals to the Transceiver Reconfiguration Controller.
4 The Bitec HDMI HSMC 2.0 daughter card routes the TMDS clock pin to the transceiver serial data pin. To use the TMDS clock to drive the HDMI PLL, the TMDS clock must also drive the transceiver dedicated reference clock pin. The number of CDR reference clocks is 2 with reference clock 1 (unused) driven by the TMDS clock and reference clock 0 driven by the HDMI PLL output clock. The selected CDR reference clock will be fixed at 0.
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