Visible to Intel only — GUID: vgo1401781698432
Ixiasoft
1. HDMI Intel® FPGA IP Quick Reference
2. HDMI Overview
3. HDMI Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI Source
6. HDMI Sink
7. HDMI Parameters
8. HDMI Simulation Example
9. HDMI Intel® FPGA IP User Guide Archives
10. Document Revision History for the HDMI Intel® FPGA IP User Guide
4.3.1.1. Transceiver Native PHY (RX)
4.3.1.2. PLL Intel FPGA IP Cores
4.3.1.3. PLL Reconfig Intel FPGA IP Core
4.3.1.4. Multirate Reconfig Controller (RX)
4.3.1.5. Oversampler (RX)
4.3.1.6. DCFIFO
4.3.1.7. Sink Display Data Channel (DDC) & Status and Control Data Channel (SCDC)
4.3.1.8. Transceiver Reconfiguration Controller
4.3.1.9. VIP Bypass and Audio, Auxiliary and InfoFrame Buffers
4.3.1.10. Transceiver Native PHY (TX)
4.3.1.11. Transceiver PHY Reset Controller
4.3.1.12. Oversampler (TX)
4.3.1.13. Clock Enable Generator
4.3.1.14. Platform Designer System
5.1. Source Functional Description
5.2. Source Interfaces
5.3. Source Clock Tree
5.4. Link Training Procedure
5.5. FRL Clocking Scheme
5.6. Valid Video Data
5.7. Source Deep Color Implementation When Support FRL = 0
5.8. Source Deep Color Implementation When Support FRL = 1
5.9. Variable Refresh Rate (VRR) and Auto Low Latency Mode (ALLM)
5.1.1. Source Scrambler, TMDS/TERC4 Encoder
5.1.2. Source Video Resampler
5.1.3. Source Window of Opportunity Generator
5.1.4. Source Auxiliary Packet Encoder
5.1.5. Source Auxiliary Packet Generators
5.1.6. Source Auxiliary Data Path Multiplexers
5.1.7. Source Auxiliary Control Port
5.1.8. Source Audio Encoder
5.1.9. HDCP 1.4 TX Architecture
5.1.10. HDCP 2.3 TX Architecture
5.1.11. FRL Packetizer
5.1.12. FRL Character Block and Super Block Mapping
5.1.13. Reed-Solomon (RS) Forward Error Correction (FEC) Generation and Insertion
5.1.14. FRL Scrambler and Encoder
5.1.15. Source FRL Resampler
5.1.16. TX Oversampler
5.1.17. Clock Enable Generator
5.1.18. I2C Master
6.1.1. Sink Word Alignment and Channel Deskew
6.1.2. Sink Descrambler, TMDS/TERC4 Decoder
6.1.3. Sink Auxiliary Decoder
6.1.4. Sink Auxiliary Packet Capture
6.1.5. Sink Video Resampler
6.1.6. Sink Auxiliary Data Port
6.1.7. Sink Audio Decoder
6.1.8. Status and Control Data Channel (SCDC) Interface
6.1.9. HDCP 1.4 RX Architecture
6.1.10. HDCP 2.3 RX Architecture
6.1.11. FRL Depacketizer
6.1.12. Sink FRL Character Block and Super Block Demapper
6.1.13. Sink FRL Descrambler and Decoder
6.1.14. Sink FRL Resampler
6.1.15. RX Oversampler
6.1.16. I2C Slave
6.1.17. I2C and EDID RAM Blocks
6.1.18. Variable Refresh Rate(VRR) and Auto Low Latency Mode (ALLM)
Visible to Intel only — GUID: vgo1401781698432
Ixiasoft
1. HDMI Intel® FPGA IP Quick Reference
Updated for: |
---|
Intel® Quartus® Prime Design Suite 21.3 |
IP Version 19.6.1 |
The Intel® FPGA High-Definition Multimedia Interface (HDMI) IP provides support for next-generation video display interface technology.
The HDMI Intel® FPGA IP is part of the Intel® FPGA IP Library, which is distributed with the Intel® Quartus® Prime software.
Note: All information in this document refers to the Intel® Quartus® Prime Pro Edition software, unless stated otherwise.
Information | Description | |
---|---|---|
IP Information | Core Features |
|
Typical Application |
|
|
Device Family | Supports Intel® Stratix® 10 (H-tile and L-tile), Intel® Arria® 10, Intel® Cyclone® 10 GX, Arria® V, and Stratix® V FPGA devices
Note: HDMI 2.1 with FRL enabled supports only Intel® Stratix® 10 and Intel® Arria® 10 devices.
|
|
Design Tools |
|
Note: The High-bandwidth Digital Content Protection (HDCP) feature is not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.