HDMI Intel® FPGA IP User Guide

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ID 683798
Date 11/12/2021
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Quick Reference 2. HDMI Overview 3. HDMI Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI Source 6. HDMI Sink 7. HDMI Parameters 8. HDMI Simulation Example 9. HDMI Intel® FPGA IP User Guide Archives 10. Document Revision History for the HDMI Intel® FPGA IP User Guide
2. HDMI Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel Arria 10, Intel Cyclone 10 GX, and Intel Stratix 10 Devices 4.2. HDCP Over HDMI Design Example for Intel® Arria® 10 and Intel® Stratix® 10 Devices 4.3. HDMI Hardware Design Examples for Arria V and Stratix V Devices
4.3. HDMI Hardware Design Examples for Arria V and Stratix V Devices x
4.3.1. HDMI Hardware Design Components 4.3.2. HDMI Hardware Design Requirements 4.3.3. Design Walkthrough
4.3.1. HDMI Hardware Design Components x
4.3.1.1. Transceiver Native PHY (RX) 4.3.1.2. PLL Intel FPGA IP Cores 4.3.1.3. PLL Reconfig Intel FPGA IP Core 4.3.1.4. Multirate Reconfig Controller (RX) 4.3.1.5. Oversampler (RX) 4.3.1.6. DCFIFO 4.3.1.7. Sink Display Data Channel (DDC) & Status and Control Data Channel (SCDC) 4.3.1.8. Transceiver Reconfiguration Controller 4.3.1.9. VIP Bypass and Audio, Auxiliary and InfoFrame Buffers 4.3.1.10. Transceiver Native PHY (TX) 4.3.1.11. Transceiver PHY Reset Controller 4.3.1.12. Oversampler (TX) 4.3.1.13. Clock Enable Generator 4.3.1.14. Platform Designer System
4.3.1.14. Platform Designer System x
4.3.1.14.1. VIP Passthrough for HDMI Video Stream 4.3.1.14.2. Source SCDC Controller 4.3.1.14.3. Source Reconfiguration Controller
4.3.3. Design Walkthrough x
4.3.3.1. Set Up the Hardware 4.3.3.2. Copy the Design Files 4.3.3.3. Build and Compile the Design 4.3.3.4. View the Results
4.3.3.4. View the Results x
4.3.3.4.1. Push Buttons, DIP Switches and LED Functions
5. HDMI Source x
5.1. Source Functional Description 5.2. Source Interfaces 5.3. Source Clock Tree 5.4. Link Training Procedure 5.5. FRL Clocking Scheme 5.6. Valid Video Data 5.7. Source Deep Color Implementation When Support FRL = 0 5.8. Source Deep Color Implementation When Support FRL = 1 5.9. Variable Refresh Rate (VRR) and Auto Low Latency Mode (ALLM)
5.1. Source Functional Description x
5.1.1. Source Scrambler, TMDS/TERC4 Encoder 5.1.2. Source Video Resampler 5.1.3. Source Window of Opportunity Generator 5.1.4. Source Auxiliary Packet Encoder 5.1.5. Source Auxiliary Packet Generators 5.1.6. Source Auxiliary Data Path Multiplexers 5.1.7. Source Auxiliary Control Port 5.1.8. Source Audio Encoder 5.1.9. HDCP 1.4 TX Architecture 5.1.10. HDCP 2.3 TX Architecture 5.1.11. FRL Packetizer 5.1.12. FRL Character Block and Super Block Mapping 5.1.13. Reed-Solomon (RS) Forward Error Correction (FEC) Generation and Insertion 5.1.14. FRL Scrambler and Encoder 5.1.15. Source FRL Resampler 5.1.16. TX Oversampler 5.1.17. Clock Enable Generator 5.1.18. I2C Master
5.1.7. Source Auxiliary Control Port x
5.1.7.1. Source General Control Packet (GCP) 5.1.7.2. Source Auxiliary Video Information (AVI) InfoFrame Bit-Fields 5.1.7.3. Source HDMI Vendor Specific InfoFrame (VSI)
5.1.8. Source Audio Encoder x
5.1.8.1. Audio InfoFrame (AI) Bundle Bit-Fields 5.1.8.2. Audio Metadata Bundle Bit-Fields
6. HDMI Sink x
6.1. Sink Functional Description 6.2. Sink Interfaces 6.3. Sink Clock Tree 6.4. Link Training Procedure 6.5. Sink Deep Color Implementation When Support FRL = 0 6.6. Sink Deep Color Implementation When Support FRL = 1
6.1. Sink Functional Description x
6.1.1. Sink Word Alignment and Channel Deskew 6.1.2. Sink Descrambler, TMDS/TERC4 Decoder 6.1.3. Sink Auxiliary Decoder 6.1.4. Sink Auxiliary Packet Capture 6.1.5. Sink Video Resampler 6.1.6. Sink Auxiliary Data Port 6.1.7. Sink Audio Decoder 6.1.8. Status and Control Data Channel (SCDC) Interface 6.1.9. HDCP 1.4 RX Architecture 6.1.10. HDCP 2.3 RX Architecture 6.1.11. FRL Depacketizer 6.1.12. Sink FRL Character Block and Super Block Demapper 6.1.13. Sink FRL Descrambler and Decoder 6.1.14. Sink FRL Resampler 6.1.15. RX Oversampler 6.1.16. I2C Slave 6.1.17. I2C and EDID RAM Blocks 6.1.18. Variable Refresh Rate(VRR) and Auto Low Latency Mode (ALLM)
6.1.6. Sink Auxiliary Data Port x
6.1.6.1. Sink General Control Packet (GCP) 6.1.6.2. Sink Auxiliary Video Information (AVI) InfoFrame Bit-Fields 6.1.6.3. Sink HDMI Vendor Specific InfoFrame (VSI)
6.1.7. Sink Audio Decoder x
6.1.7.1. Audio InfoFrame (AI) Bundle Bit-Fields 6.1.7.2. Audio Metadata Bundle Bit-Fields
7. HDMI Parameters x
7.1. HDMI Source Parameters 7.2. HDMI Sink Parameters
8. HDMI Simulation Example x
8.1. Simulation Walkthrough
1. HDMI Intel® FPGA IP Quick Reference
2. HDMI Overview
3. HDMI Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI Source
6. HDMI Sink
7. HDMI Parameters
8. HDMI Simulation Example
9. HDMI Intel® FPGA IP User Guide Archives
10. Document Revision History for the HDMI Intel® FPGA IP User Guide

2.4. Resource Utilization

The resource utilization data indicates typical expected performance for the HDMI Intel® FPGA IP in the Intel® Quartus® Prime Pro Edition software.
Table 5.  HDMI Data RateThe table lists the maximum data rates for HDMI Intel® FPGA IP configurations.
Devices Maximum Data Rate (Mbps)
2 Pixels per Clock

(Support FRL = 0)

 8 Pixels per Clock

(Support FRL = 1)
Intel® Stratix® 10 5,940

(Example: 4Kp60 8 bpc)

 12,000

(Example: 8Kp30 12 bpc)
Intel® Arria® 10 5,940

(Example: 4Kp60 8 bpc)

 12,000

(Example: 8Kp30 12 bpc)
Intel® Cyclone® 10 GX 5,940

(Example: 4Kp60 8 bpc)

 Not Supported
Table 6.   HDMI Intel® FPGA IP Resource UtilizationThe table lists the performance data for the different Intel FPGA devices.
Device Pixels per Clock Direction ALMs Logic Registers Memory
Primary Secondary Bits M10K or M20K
Intel® Stratix® 10 H-tile

(Support FRL = 0)

1 		2 RX 5.041 6,633 902 38,400 14
2 TX 4,975 7,559 1,368 37,568 13
Intel® Stratix® 10 L-tile

(Support FRL = 0)

1 		2 RX 5,025 6,584 967 38,400 14
2 TX 4,966 7,539 1,425 37,568 13
Intel® Arria® 10

(Support FRL = 0)

1 		2 RX 3,768 5,716 1,049 36,352 14
2 TX 4,445 7,016 1,701 36,968 13
Intel® Arria® 10

(Support FRL = 1)2

8 RX 48,865 55,417 13,067 376,832 87
8 TX 30,092 35,533 6,839 276,288 60
Intel® Cyclone® 10 GX 2 RX 4,000 5,768 965 38,400 14
2 TX 4,484 7,167 1,629 36,968 13
Table 7.  Recommended Speed Grades for Intel® Stratix® 10 and Intel® Arria® 10 Devices (Support FRL = 1)
Device Lane Rate (Mbps) Transceiver Interface Width (bits) Speed Grade
Intel® Stratix® 10 12,000 40 -1, -2 3
Intel® Arria® 10 12,000 40 -1, -2
Table 8.  Recommended Speed Grades for Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX Devices (Support FRL = 0)
Device Lane Rate (Mbps) Interface Width (bits) Speed Grades
Intel® Stratix® 10 6,000 20 -1, -2
Intel® Arria® 10 6,000 20 -1, -2
Intel® Cyclone® 10 GX 6,000 20 -5
Table 9.  HDCP Resource UtilizationThe table lists the HDCP resource data for Intel® Arria® 10 and Intel® Stratix® 10 devices.
Device HDCP IP Support HDCP Key Management Support FRL Pixels/TMDS Symbols Per Clock ALMs Combinational ALUTs Registers M20K DSP
Intel® Arria® 10 HDCP 2.3 TX 0 0 2 6,479 10,548 12,015 10 3
1 8 16,629 28,783 23,606 10 3
1 0 2 6,875 11,338 12,793 12 3
1 8 17,048 29,534 24,367 12 3
HDCP 2.3 RX 0 0 2 7,119 11,685 12,673 11 3
1 8 17,083 30,148 24,068 11 3
1 0 2 7,543 12,420 13,406 13 3
1 8 17,552 30,861 24,806 13 3
HDCP 1.4 TX 0 0, 1 2 1,665 2,626 4,411 2 0
1 0, 1 2 2,142 3,411 5,167 4 0
HDCP 1.4 RX 0 0, 1 2 1,170 1,850 3,407 3 0
1 0, 1 2 1,616 2,558 4,207 5 0
Intel® Stratix® 10 HDCP 2.3 TX 0 0 2 7,213 11,582 12,810 10 3
1 8 17,755 29,784 24,428 10 3
1 0 2 7,888 12,473 13,188 12 3
1 8 18,477 30,540 25,191 12 3
HDCP 2.3 RX 0 0 2 8,145 12,691 13,438 11 3
1 8 18,482 30,881 25,422 11 3
1 0 2 8,644 13,382 13,640 13 3
1 8 19,096 31,460 26,138 13 3
HDCP 1.4 TX 0 0, 1 2 2,320 2,937 4,544 2 0
1 0, 1 2 2,881 3,797 5,170 4 0
HDCP 1.4 RX 0 0, 1 2 1,784 2,135 3,605 3 0
1 0, 1 2 2,293 2,897 4,219 5 0
1 Resource data for Support FRL = 1 design is not finalized.
2 Contact Intel Sales for further optimization for specific device variants.
3 Contact Intel Sales if you need to use -2 speed grade.
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