HDMI Intel® FPGA IP User Guide

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ID 683798
Date 11/12/2021
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Quick Reference 2. HDMI Overview 3. HDMI Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI Source 6. HDMI Sink 7. HDMI Parameters 8. HDMI Simulation Example 9. HDMI Intel® FPGA IP User Guide Archives 10. Document Revision History for the HDMI Intel® FPGA IP User Guide
2. HDMI Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel Arria 10, Intel Cyclone 10 GX, and Intel Stratix 10 Devices 4.2. HDCP Over HDMI Design Example for Intel® Arria® 10 and Intel® Stratix® 10 Devices 4.3. HDMI Hardware Design Examples for Arria V and Stratix V Devices
4.3. HDMI Hardware Design Examples for Arria V and Stratix V Devices x
4.3.1. HDMI Hardware Design Components 4.3.2. HDMI Hardware Design Requirements 4.3.3. Design Walkthrough
4.3.1. HDMI Hardware Design Components x
4.3.1.1. Transceiver Native PHY (RX) 4.3.1.2. PLL Intel FPGA IP Cores 4.3.1.3. PLL Reconfig Intel FPGA IP Core 4.3.1.4. Multirate Reconfig Controller (RX) 4.3.1.5. Oversampler (RX) 4.3.1.6. DCFIFO 4.3.1.7. Sink Display Data Channel (DDC) & Status and Control Data Channel (SCDC) 4.3.1.8. Transceiver Reconfiguration Controller 4.3.1.9. VIP Bypass and Audio, Auxiliary and InfoFrame Buffers 4.3.1.10. Transceiver Native PHY (TX) 4.3.1.11. Transceiver PHY Reset Controller 4.3.1.12. Oversampler (TX) 4.3.1.13. Clock Enable Generator 4.3.1.14. Platform Designer System
4.3.1.14. Platform Designer System x
4.3.1.14.1. VIP Passthrough for HDMI Video Stream 4.3.1.14.2. Source SCDC Controller 4.3.1.14.3. Source Reconfiguration Controller
4.3.3. Design Walkthrough x
4.3.3.1. Set Up the Hardware 4.3.3.2. Copy the Design Files 4.3.3.3. Build and Compile the Design 4.3.3.4. View the Results
4.3.3.4. View the Results x
4.3.3.4.1. Push Buttons, DIP Switches and LED Functions
5. HDMI Source x
5.1. Source Functional Description 5.2. Source Interfaces 5.3. Source Clock Tree 5.4. Link Training Procedure 5.5. FRL Clocking Scheme 5.6. Valid Video Data 5.7. Source Deep Color Implementation When Support FRL = 0 5.8. Source Deep Color Implementation When Support FRL = 1 5.9. Variable Refresh Rate (VRR) and Auto Low Latency Mode (ALLM)
5.1. Source Functional Description x
5.1.1. Source Scrambler, TMDS/TERC4 Encoder 5.1.2. Source Video Resampler 5.1.3. Source Window of Opportunity Generator 5.1.4. Source Auxiliary Packet Encoder 5.1.5. Source Auxiliary Packet Generators 5.1.6. Source Auxiliary Data Path Multiplexers 5.1.7. Source Auxiliary Control Port 5.1.8. Source Audio Encoder 5.1.9. HDCP 1.4 TX Architecture 5.1.10. HDCP 2.3 TX Architecture 5.1.11. FRL Packetizer 5.1.12. FRL Character Block and Super Block Mapping 5.1.13. Reed-Solomon (RS) Forward Error Correction (FEC) Generation and Insertion 5.1.14. FRL Scrambler and Encoder 5.1.15. Source FRL Resampler 5.1.16. TX Oversampler 5.1.17. Clock Enable Generator 5.1.18. I2C Master
5.1.7. Source Auxiliary Control Port x
5.1.7.1. Source General Control Packet (GCP) 5.1.7.2. Source Auxiliary Video Information (AVI) InfoFrame Bit-Fields 5.1.7.3. Source HDMI Vendor Specific InfoFrame (VSI)
5.1.8. Source Audio Encoder x
5.1.8.1. Audio InfoFrame (AI) Bundle Bit-Fields 5.1.8.2. Audio Metadata Bundle Bit-Fields
6. HDMI Sink x
6.1. Sink Functional Description 6.2. Sink Interfaces 6.3. Sink Clock Tree 6.4. Link Training Procedure 6.5. Sink Deep Color Implementation When Support FRL = 0 6.6. Sink Deep Color Implementation When Support FRL = 1
6.1. Sink Functional Description x
6.1.1. Sink Word Alignment and Channel Deskew 6.1.2. Sink Descrambler, TMDS/TERC4 Decoder 6.1.3. Sink Auxiliary Decoder 6.1.4. Sink Auxiliary Packet Capture 6.1.5. Sink Video Resampler 6.1.6. Sink Auxiliary Data Port 6.1.7. Sink Audio Decoder 6.1.8. Status and Control Data Channel (SCDC) Interface 6.1.9. HDCP 1.4 RX Architecture 6.1.10. HDCP 2.3 RX Architecture 6.1.11. FRL Depacketizer 6.1.12. Sink FRL Character Block and Super Block Demapper 6.1.13. Sink FRL Descrambler and Decoder 6.1.14. Sink FRL Resampler 6.1.15. RX Oversampler 6.1.16. I2C Slave 6.1.17. I2C and EDID RAM Blocks 6.1.18. Variable Refresh Rate(VRR) and Auto Low Latency Mode (ALLM)
6.1.6. Sink Auxiliary Data Port x
6.1.6.1. Sink General Control Packet (GCP) 6.1.6.2. Sink Auxiliary Video Information (AVI) InfoFrame Bit-Fields 6.1.6.3. Sink HDMI Vendor Specific InfoFrame (VSI)
6.1.7. Sink Audio Decoder x
6.1.7.1. Audio InfoFrame (AI) Bundle Bit-Fields 6.1.7.2. Audio Metadata Bundle Bit-Fields
7. HDMI Parameters x
7.1. HDMI Source Parameters 7.2. HDMI Sink Parameters
8. HDMI Simulation Example x
8.1. Simulation Walkthrough
1. HDMI Intel® FPGA IP Quick Reference
2. HDMI Overview
3. HDMI Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI Source
6. HDMI Sink
7. HDMI Parameters
8. HDMI Simulation Example
9. HDMI Intel® FPGA IP User Guide Archives
10. Document Revision History for the HDMI Intel® FPGA IP User Guide

7.2. HDMI Sink Parameters

Table 62.  HDMI Sink Parameters
Parameter Value Description
Device family

Intel® Stratix® 10

Intel® Arria® 10

Intel® Cyclone® 10 GX

Arria V

Stratix V

 Targeted device family. This parameter inherits the value from the project device.
Direction

Transmitter

Receiver

 Select HDMI receiver.
Pixels per clock 2 or 8 pixels per clock

Determines how many pixels are processed per clock.

  • When you turn off Support FRL, supports 2 pixels per clock.
  • When you turn on Support FRL, supports 8 pixels per clock.
Note: This parameter is available only with Intel® Arria® 10 and Intel® Stratix® 10 devices.
Transceiver width 20 or 40 bits Determines the required transceiver width. The transceiver width depends on the number of TMDS symbols processed in parallel (symbols per clock).
  • When you turn off Support FRL, transceiver width is 20 bits (2 symbols per clock).
  • When you turn on Support FRL, transceiver width is 40 bits (4 symbols per clock).
Note: This parameter is available only with Intel® Arria® 10 and Intel® Stratix® 10 devices.
Support auxiliary On, Off Determines if auxiliary channel encoding is included. This parameter is turned on by default.

This parameter is always turned on when Support FRL is enabled.
Support deep color On, Off

Determines if the core can encode deep color formats. This parameter is turned on by default.
Support audio On, Off

Determines if the core can encode audio data.

To enable this parameter, you must also enable the Support auxiliary parameter. This parameter is turned on by default.

Support FRL On, Off

Turn on to enable the FRL path.

When enabled, the clock domains for the auxiliary and audio ports, and the internal modules are different Refer to the block diagram for more details.

Note: This parameter is available only with Intel® Arria® 10 and Intel® Stratix® 10 devices.
Support HDCP 1.4 On, Off

Turn on to enable HDCP 1.4 RX support. This parameter can only be used with Intel® Arria® 10 and Intel® Stratix® 10 devices.

Note: The HDCP-related parameters are not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.
Support HDCP 2.3 On, Off

Turn on to enable HDCP 2.3 RX support. This parameter can only be used with Intel® Arria® 10 and Intel® Stratix® 10 devices.

Note: The HDCP-related parameters are not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.
Support HDCP Key Management On, Off Turn on to enable HDCP key management support. You can only turn on this parameter if you turn on the Support HDCP 1.4 or Support HDCP 2.3 parameters.
Note:
  1. The HDCP-related parameters are not included in the Intel Quartus Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.
  2. The HDCP key management support from version 21.3 onwards is not compatible with the KEYENC version 21.2 and earlier. You need to re-encrypt the HDCP production keys using the KEYENC version 21.3 onwards. Refer to HDMI Intel Arria 10 FPGA IP Design Example User Guide and HDMI Intel Stratix 10 FPGA IP Design Example User Guide for more details.
Manufacturer OUI —

The Manufacturer Organizationally Unique Identifier (OUI) assigned to the manufactured device to be written into the SCDC registers of address 0xD0, 0xD1, and 0xD2.

Key in 3 byte hexadecimal data.
Device ID String —

The Device Identification (ID) string to be written into the SCDC registers from addresses 0xD3 to 0xDa.

Use this parameter to identify the sink device. You can key in up to eight ASCII characters. If you use less than eight characters, the unused bytes are set to 0x00.

Hardware Revision —

Indicates the major and minor revisions of the hardware. Key in one byte of integer data.

  • Upper byte represents major revision.
  • Lower byte represents minor revision.

The hardware major revision increments on a major silicon or board revision. The hardware minor revision increments on a minor silicon revision or minor board revision and resets to 0 when the major revision increments.

Include I2C slave On, Off

Turn on to include a pair of I2C slaves for EDID and SCDC registers. path.

Include EDID RAM On, Off

Turn on to include RAM to store EDID information for RX.

Note: You can only turn on this parameter if you turned on the Include I2C slave parameter.
EDID RAM size In multiple of 2N

Specifies the memory size in number of N-bit words. The value must be in multiple of 2N.

For example, the default memory size is 256 words which is 28 with N = 8.

The N also determines the width of the address bus of the RAM’s Avalon® memory-mapped nterface.

Note: This parameter is enabled only if you turned on the Include EDID RAM parameter.
RAM file path –

Initial content of the memory. The file must be in .hex or .mif file type.

Note: This parameter is enabled only if you turned on the Include EDID RAM parameter.
HPD signal polarity 0, 1 Specifies the polarity of Hot Plug Detect (HPD) signal from the connector.
  • 0: Negative
  • 1: Positive
Note: For Bitec daughter card, always set the polarity to 0.
Include I2C Master/Slave On, Off

Turn on to include I2C master on the HDMI TX or I2C slave on the HDMI RX for the DDC channel communication.

When enabled for RX, HDMI RX core includes I2C slave with I2C serial interface exposed for the connection to the HDMI connector. I2C slave is driven internally by EDID RAM and SCDC register.

When enabled for TX, HDMI TX core includes I2C master with I2C serial interface exposed for the connection to the HDMI connector. I2C master will also expose Avalon-MM interface for the user control using NIOS.

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