HDMI Intel® FPGA IP User Guide

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ID 683798
Date 11/12/2021
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Quick Reference 2. HDMI Overview 3. HDMI Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI Source 6. HDMI Sink 7. HDMI Parameters 8. HDMI Simulation Example 9. HDMI Intel® FPGA IP User Guide Archives 10. Document Revision History for the HDMI Intel® FPGA IP User Guide
2. HDMI Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel Arria 10, Intel Cyclone 10 GX, and Intel Stratix 10 Devices 4.2. HDCP Over HDMI Design Example for Intel® Arria® 10 and Intel® Stratix® 10 Devices 4.3. HDMI Hardware Design Examples for Arria V and Stratix V Devices
4.3. HDMI Hardware Design Examples for Arria V and Stratix V Devices x
4.3.1. HDMI Hardware Design Components 4.3.2. HDMI Hardware Design Requirements 4.3.3. Design Walkthrough
4.3.1. HDMI Hardware Design Components x
4.3.1.1. Transceiver Native PHY (RX) 4.3.1.2. PLL Intel FPGA IP Cores 4.3.1.3. PLL Reconfig Intel FPGA IP Core 4.3.1.4. Multirate Reconfig Controller (RX) 4.3.1.5. Oversampler (RX) 4.3.1.6. DCFIFO 4.3.1.7. Sink Display Data Channel (DDC) & Status and Control Data Channel (SCDC) 4.3.1.8. Transceiver Reconfiguration Controller 4.3.1.9. VIP Bypass and Audio, Auxiliary and InfoFrame Buffers 4.3.1.10. Transceiver Native PHY (TX) 4.3.1.11. Transceiver PHY Reset Controller 4.3.1.12. Oversampler (TX) 4.3.1.13. Clock Enable Generator 4.3.1.14. Platform Designer System
4.3.1.14. Platform Designer System x
4.3.1.14.1. VIP Passthrough for HDMI Video Stream 4.3.1.14.2. Source SCDC Controller 4.3.1.14.3. Source Reconfiguration Controller
4.3.3. Design Walkthrough x
4.3.3.1. Set Up the Hardware 4.3.3.2. Copy the Design Files 4.3.3.3. Build and Compile the Design 4.3.3.4. View the Results
4.3.3.4. View the Results x
4.3.3.4.1. Push Buttons, DIP Switches and LED Functions
5. HDMI Source x
5.1. Source Functional Description 5.2. Source Interfaces 5.3. Source Clock Tree 5.4. Link Training Procedure 5.5. FRL Clocking Scheme 5.6. Valid Video Data 5.7. Source Deep Color Implementation When Support FRL = 0 5.8. Source Deep Color Implementation When Support FRL = 1 5.9. Variable Refresh Rate (VRR) and Auto Low Latency Mode (ALLM)
5.1. Source Functional Description x
5.1.1. Source Scrambler, TMDS/TERC4 Encoder 5.1.2. Source Video Resampler 5.1.3. Source Window of Opportunity Generator 5.1.4. Source Auxiliary Packet Encoder 5.1.5. Source Auxiliary Packet Generators 5.1.6. Source Auxiliary Data Path Multiplexers 5.1.7. Source Auxiliary Control Port 5.1.8. Source Audio Encoder 5.1.9. HDCP 1.4 TX Architecture 5.1.10. HDCP 2.3 TX Architecture 5.1.11. FRL Packetizer 5.1.12. FRL Character Block and Super Block Mapping 5.1.13. Reed-Solomon (RS) Forward Error Correction (FEC) Generation and Insertion 5.1.14. FRL Scrambler and Encoder 5.1.15. Source FRL Resampler 5.1.16. TX Oversampler 5.1.17. Clock Enable Generator 5.1.18. I2C Master
5.1.7. Source Auxiliary Control Port x
5.1.7.1. Source General Control Packet (GCP) 5.1.7.2. Source Auxiliary Video Information (AVI) InfoFrame Bit-Fields 5.1.7.3. Source HDMI Vendor Specific InfoFrame (VSI)
5.1.8. Source Audio Encoder x
5.1.8.1. Audio InfoFrame (AI) Bundle Bit-Fields 5.1.8.2. Audio Metadata Bundle Bit-Fields
6. HDMI Sink x
6.1. Sink Functional Description 6.2. Sink Interfaces 6.3. Sink Clock Tree 6.4. Link Training Procedure 6.5. Sink Deep Color Implementation When Support FRL = 0 6.6. Sink Deep Color Implementation When Support FRL = 1
6.1. Sink Functional Description x
6.1.1. Sink Word Alignment and Channel Deskew 6.1.2. Sink Descrambler, TMDS/TERC4 Decoder 6.1.3. Sink Auxiliary Decoder 6.1.4. Sink Auxiliary Packet Capture 6.1.5. Sink Video Resampler 6.1.6. Sink Auxiliary Data Port 6.1.7. Sink Audio Decoder 6.1.8. Status and Control Data Channel (SCDC) Interface 6.1.9. HDCP 1.4 RX Architecture 6.1.10. HDCP 2.3 RX Architecture 6.1.11. FRL Depacketizer 6.1.12. Sink FRL Character Block and Super Block Demapper 6.1.13. Sink FRL Descrambler and Decoder 6.1.14. Sink FRL Resampler 6.1.15. RX Oversampler 6.1.16. I2C Slave 6.1.17. I2C and EDID RAM Blocks 6.1.18. Variable Refresh Rate(VRR) and Auto Low Latency Mode (ALLM)
6.1.6. Sink Auxiliary Data Port x
6.1.6.1. Sink General Control Packet (GCP) 6.1.6.2. Sink Auxiliary Video Information (AVI) InfoFrame Bit-Fields 6.1.6.3. Sink HDMI Vendor Specific InfoFrame (VSI)
6.1.7. Sink Audio Decoder x
6.1.7.1. Audio InfoFrame (AI) Bundle Bit-Fields 6.1.7.2. Audio Metadata Bundle Bit-Fields
7. HDMI Parameters x
7.1. HDMI Source Parameters 7.2. HDMI Sink Parameters
8. HDMI Simulation Example x
8.1. Simulation Walkthrough
1. HDMI Intel® FPGA IP Quick Reference
2. HDMI Overview
3. HDMI Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI Source
6. HDMI Sink
7. HDMI Parameters
8. HDMI Simulation Example
9. HDMI Intel® FPGA IP User Guide Archives
10. Document Revision History for the HDMI Intel® FPGA IP User Guide

6.1.9. HDCP 1.4 RX Architecture

The HDCP 1.4 receiver block decrypts the protected video and auxiliary data from the connected HDCP 1.4 device. The HDCP 1.4 receiver block has identical structure layers as the HDCP 1.4 transmitter block.
Figure 51. Architecture Block Diagram of HDCP 1.4 RX IP

The HDCP 1.4 RX core is fully autonomous. For HDMI application, the transmitter drives the HDCP 1.4 RX core using the standard DDC interface supporting I2C protocol. You need an I2C slave externally to drive the IP through the HDCP Register Port (Avalon-MM).

The HDCP specifications requires the HDCP 2.3 RX core to be programmed with the DCP-issued production key – Device Private Keys (Bkeys) and Key Selection Vector (Bksv). The IP retrieves the key from the on-chip memory externally to the core through the HDCP Key Port. The on-chip memory must store the key data in the arrangement shown in the table below.

Table 53.  HDCP 1.4 RX Key Port Addressing
Address Content
6'h28 {16’d0, Bksv[39:0]}
6'h27 Bkeys39[55:0]
6'h26 Bkeys38[55:0]
... ...
6'h01 Bkeys01[55:0]
6'h00 Bkeys00[55:0]

The Video Stream and Auxiliary Layer receives audio and video content over its Video and Aux Data Input Port, and performs the decryption operation. The Video Stream and Auxiliary Layer detects the Encryption Status Signaling (ESS) provided by the HDMI IP to determine when to decrypt frames.

To implement the HDCP 1.4 RX core as a repeater upstream interface, the IP must propagate certain information such as KSV list and Bstatus to the upstream transmitter and to be used for SHA-1 hash digest. The repeater downstream interface (TX) must provide this information using the Repeater Message Port (Avalon-MM). You can use the same clock source to drive the clocking for the HDCP Register Port and Repeater Message Port.

The RX registers mapping defined in the following table is equivalent to the address space for HDCP 1.4 receiver defined in the HDCP specification.

Table 54.  HDCP 1.4 RX Registers Mapping
Address Register R/W Reset Bit Bit Name Description
0x00 BKSV0 RO - 7:0 - Bit [7:0] of HDCP Receiver KSV.
0x01 BKSV1 - 7:0 Bit [15:8] of HDCP Receiver KSV.
0x02 BKSV2 - 7:0 Bit [23:16] of HDCP Receiver KSV.
0x03 BKSV3 - 7:0 Bit [31:24] of HDCP Receiver KSV.
0x04 BKSV4 - 7:0 Bit [39:32] of HDCP Receiver KSV.
0x05-0x07 Rsvd RO 0x00 7:0 - Reserved. All bytes read as 0x00.
0x08 RI_PRIME0 RO 0x00 7:0 - Link verification response. Bit [7:0] of Ri’.
0x09 RI_PRIME1 0x00 7:0 - Link verification response. Bit [15:8] of Ri’.
0x0A PJ_PRIME RO 0x00 7:0 - Reserved. All bytes read as 0x00.
0x0B – 0x0F Rsvd RO 0x00 7:0 - Reserved. All bytes read as 0x00.
0x10 AKSV0 WO 0x00 7:0 - Bit [7:0] of HDCP Transmitter KSV.
0x11 AKSV1 0x00 7:0 Bit [15:8] of HDCP Transmitter KSV.
0x12 AKSV2 0x00 7:0 Bit [23:16] of HDCP Transmitter KSV.
0x13 AKSV3 0x00 7:0 Bit [31:24] of HDCP Transmitter KSV.
0x14 AKSV4 0x00 7:0 Bit [39:32] of HDCP Transmitter KSV.
0x15 AINFO WO 0x00 7:0 - Reserved.
0x16 – 0x17 Rsvd RO 0x00 7:0 - Reserved. All bytes read as 0x00.
0x18 AN0 WO 0x00 7:0 - Bit [7:0] of HDCP Session Random Number An.
0x19 AN1 0x00 7:0 Bit [15:8] of HDCP Session Random Number An.
0x1A AN2 0x00 7:0 Bit [23:16] of HDCP Session Random Number An.
0x1B AN3 0x00 7:0 Bit [31:24] of HDCP Session Random Number An.
0x1C AN4 0x00 7:0 Bit [39:32] of HDCP Session Random Number An.
0x1D AN5 0x00 7:0 Bit [47:40] of HDCP Session Random Number An.
0x1E AN6 0x00 7:0 Bit [55:48] of HDCP Session Random Number An.
0x1F AN7 0x00 7:0 Bit [63:56] of HDCP Session Random Number An.
0x20 V_PRIME_H0_0 RO 0x00 7:0 - H0 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H0 value.
0x21 V_PRIME_H0_1 0x00 7:0 Bit [15:8] of H0 value.
0x22 V_PRIME_H0_2 0x00 7:0 Bit [23:16] of H0 value.
0x23 V_PRIME_H0_3 0x00 7:0 Bit [31:24] of H0 value.
0x24 V_PRIME_H1_0 RO 0x00 7:0 - H1 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H1 value.
0x25 V_PRIME_H1_1 0x00 7:0 Bit [15:8] of H1 value.
0x26 V_PRIME_H1_2 0x00 7:0 Bit [23:16] of H1 value.
0x27 V_PRIME_H1_3 0x00 7:0 Bit [31:24] of H1 value.
0x28 V_PRIME_H2_0 RO 0x00 7:0 - H2 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H2 value.
0x29 V_PRIME_H2_1 0x00 7:0 Bit [15:8] of H2 value.
0x2A V_PRIME_H2_2 0x00 7:0 Bit [23:16] of H2 value.
0x2B V_PRIME_H2_3 0x00 7:0 Bit [31:24] of H2 value.
0x2C V_PRIME_H3_0 RO 0x00 7:0 - H3 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H3 value.
0x2D V_PRIME_H3_1 0x00 7:0 Bit [15:8] of H3 value.
0x2E V_PRIME_H3_2 0x00 7:0 Bit [23:16] of H3 value.
0x2F V_PRIME_H3_3 0x00 7:0 Bit [31:24] of H3 value.
0x30 V_PRIME_H4_0 RO 0x00 7:0 - H4 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H4 value.
0x31 V_PRIME_H4_1 0x00 7:0 Bit [15:8] of H4 value.
0x32 V_PRIME_H4_2 0x00 7:0 Bit [23:16] of H4 value.
0x33 V_PRIME_H4_3 0x00 7:0 Bit [31:24] of H4 value.
0x34 – 0x3F Rsvd RO 0x00 7:0 - Reserved. All bytes read as 00.
0x40 BCAPS RO 0x00 7 HDMI_RESERVED

0 = Receiver not capable of supporting HDMI

1 = Receiver capable of supporting HDMI
6 REPEATER

HDCP repeater capability.

0 = Receiver is not a repeater.

1 = Receiver is a repeater.
5 READY KSV FIFO ready. When set to 1, the receiver has built the list of attached KSVs and computed the verification value V’. This value is always 0 during the computation of V’.
4 FAST This bit reads as 0.
3:2 Reserved These bits read as 0.
1 FEATURES_1_1 Reserved. This bit reads as 0.
0

FAST_

REAUTHENTICATION

This bit reads as 1.
0x41 BSTATUS0 RO 0x00 7

MAX_DEVS_

EXCEEDED

Topology error indicator. When set to 1, more than 127 downstream devices, or the capacity of the KSV FIFO, are attached.
6:0 DEVICE_COUNT Total number of attached downstream devices. Always 0 for HDCP Receivers. This count does not include the HDCP Repeater itself, but only downstream devices downstream from the HDCP Repeater.
0x42 BSTATUS1 0x00 7:6 Rsvd These bits read as 0.
5 HDMI_RESERVED_2 Reserved for future possible HDMI use.
4 HDMI_MODE HDMI mode. When set to 1, the HDCP Receiver has transitioned from DVI mode to HDMI mode.
3

MAX_CASCADE_EXCEEDED

Topology error indicator. When set to 1, more than 7 levels of video repeater have been cascaded together.
2:0 DEPTH 3-bit repeater cascade depth. This value gives the number of attached levels through the connection topology.
0x43 KSV_FIFO RO 0x00 7:0 - Key selection vector FIFO. Used to pull downstream KSVs from HDCP Repeaters.
0x44 – 0xBF Rsvd RO 0x00 7:0 - Reserved. All bytes read as 0x00.
0xC0 – 0x100 DBG RW 0x00 7:0 - Implementation-specific debug registers.
Table 55.  HDCP 1.4 RX Repeater Registers Mapping
Address Register R/W Reset Bit Bit Name Description
0x00 RPT_KSV_LIST WO 0x00000000 31:8 Reserved Reserved
7:0 KSV_LIST Byte write KSV List in big endian order.
0x01 RPT_BSTATUS RW 0x00000000 31:19 Reserved Reserved
18 REQUEST Read-only. Asserted by the core to request for KSV_LIST and BSTATUS. This usually happens when re-authentication is triggered by the connected upstream. Note that when REQUEST is asserted, the READY should also be asserted.
17 READY Read-only. Asserted by the core to indicate KSV_LIST and BSTATUS are processed. Write KSV_LIST and BSTATUS after this bit is asserted.
16 VALID Set to 1 after KSV_LIST and BSTATUS are written. Self-cleared by the core after KSV_LIST and BSTATUS are read.
15:0 BSTATUS

[15:12]: Reserved.

[11]: MAX_CASCADE_EXCEEDED

[10:8]: DEPTH

[7]: MAX_DEVS_EXCEEDED

[6:0]: DEVICE_COUNT

0x02 RPT_MISC RW – 31:1 Reserved Reserved.
0 REPEATER

Set to 0 if no downstream is connected or if the connected downstream is not HDCP 1.4-capable. This means the receiver IP core is an end-point receiver rather than a repeater.

Set to 1 if the connected downstream is HDCP-capable.

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