HDMI Intel® FPGA IP User Guide

Download PDF
ID 683798
Date 11/12/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Quick Reference 2. HDMI Overview 3. HDMI Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI Source 6. HDMI Sink 7. HDMI Parameters 8. HDMI Simulation Example 9. HDMI Intel® FPGA IP User Guide Archives 10. Document Revision History for the HDMI Intel® FPGA IP User Guide
2. HDMI Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel Arria 10, Intel Cyclone 10 GX, and Intel Stratix 10 Devices 4.2. HDCP Over HDMI Design Example for Intel® Arria® 10 and Intel® Stratix® 10 Devices 4.3. HDMI Hardware Design Examples for Arria V and Stratix V Devices
4.3. HDMI Hardware Design Examples for Arria V and Stratix V Devices x
4.3.1. HDMI Hardware Design Components 4.3.2. HDMI Hardware Design Requirements 4.3.3. Design Walkthrough
4.3.1. HDMI Hardware Design Components x
4.3.1.1. Transceiver Native PHY (RX) 4.3.1.2. PLL Intel FPGA IP Cores 4.3.1.3. PLL Reconfig Intel FPGA IP Core 4.3.1.4. Multirate Reconfig Controller (RX) 4.3.1.5. Oversampler (RX) 4.3.1.6. DCFIFO 4.3.1.7. Sink Display Data Channel (DDC) & Status and Control Data Channel (SCDC) 4.3.1.8. Transceiver Reconfiguration Controller 4.3.1.9. VIP Bypass and Audio, Auxiliary and InfoFrame Buffers 4.3.1.10. Transceiver Native PHY (TX) 4.3.1.11. Transceiver PHY Reset Controller 4.3.1.12. Oversampler (TX) 4.3.1.13. Clock Enable Generator 4.3.1.14. Platform Designer System
4.3.1.14. Platform Designer System x
4.3.1.14.1. VIP Passthrough for HDMI Video Stream 4.3.1.14.2. Source SCDC Controller 4.3.1.14.3. Source Reconfiguration Controller
4.3.3. Design Walkthrough x
4.3.3.1. Set Up the Hardware 4.3.3.2. Copy the Design Files 4.3.3.3. Build and Compile the Design 4.3.3.4. View the Results
4.3.3.4. View the Results x
4.3.3.4.1. Push Buttons, DIP Switches and LED Functions
5. HDMI Source x
5.1. Source Functional Description 5.2. Source Interfaces 5.3. Source Clock Tree 5.4. Link Training Procedure 5.5. FRL Clocking Scheme 5.6. Valid Video Data 5.7. Source Deep Color Implementation When Support FRL = 0 5.8. Source Deep Color Implementation When Support FRL = 1 5.9. Variable Refresh Rate (VRR) and Auto Low Latency Mode (ALLM)
5.1. Source Functional Description x
5.1.1. Source Scrambler, TMDS/TERC4 Encoder 5.1.2. Source Video Resampler 5.1.3. Source Window of Opportunity Generator 5.1.4. Source Auxiliary Packet Encoder 5.1.5. Source Auxiliary Packet Generators 5.1.6. Source Auxiliary Data Path Multiplexers 5.1.7. Source Auxiliary Control Port 5.1.8. Source Audio Encoder 5.1.9. HDCP 1.4 TX Architecture 5.1.10. HDCP 2.3 TX Architecture 5.1.11. FRL Packetizer 5.1.12. FRL Character Block and Super Block Mapping 5.1.13. Reed-Solomon (RS) Forward Error Correction (FEC) Generation and Insertion 5.1.14. FRL Scrambler and Encoder 5.1.15. Source FRL Resampler 5.1.16. TX Oversampler 5.1.17. Clock Enable Generator 5.1.18. I2C Master
5.1.7. Source Auxiliary Control Port x
5.1.7.1. Source General Control Packet (GCP) 5.1.7.2. Source Auxiliary Video Information (AVI) InfoFrame Bit-Fields 5.1.7.3. Source HDMI Vendor Specific InfoFrame (VSI)
5.1.8. Source Audio Encoder x
5.1.8.1. Audio InfoFrame (AI) Bundle Bit-Fields 5.1.8.2. Audio Metadata Bundle Bit-Fields
6. HDMI Sink x
6.1. Sink Functional Description 6.2. Sink Interfaces 6.3. Sink Clock Tree 6.4. Link Training Procedure 6.5. Sink Deep Color Implementation When Support FRL = 0 6.6. Sink Deep Color Implementation When Support FRL = 1
6.1. Sink Functional Description x
6.1.1. Sink Word Alignment and Channel Deskew 6.1.2. Sink Descrambler, TMDS/TERC4 Decoder 6.1.3. Sink Auxiliary Decoder 6.1.4. Sink Auxiliary Packet Capture 6.1.5. Sink Video Resampler 6.1.6. Sink Auxiliary Data Port 6.1.7. Sink Audio Decoder 6.1.8. Status and Control Data Channel (SCDC) Interface 6.1.9. HDCP 1.4 RX Architecture 6.1.10. HDCP 2.3 RX Architecture 6.1.11. FRL Depacketizer 6.1.12. Sink FRL Character Block and Super Block Demapper 6.1.13. Sink FRL Descrambler and Decoder 6.1.14. Sink FRL Resampler 6.1.15. RX Oversampler 6.1.16. I2C Slave 6.1.17. I2C and EDID RAM Blocks 6.1.18. Variable Refresh Rate(VRR) and Auto Low Latency Mode (ALLM)
6.1.6. Sink Auxiliary Data Port x
6.1.6.1. Sink General Control Packet (GCP) 6.1.6.2. Sink Auxiliary Video Information (AVI) InfoFrame Bit-Fields 6.1.6.3. Sink HDMI Vendor Specific InfoFrame (VSI)
6.1.7. Sink Audio Decoder x
6.1.7.1. Audio InfoFrame (AI) Bundle Bit-Fields 6.1.7.2. Audio Metadata Bundle Bit-Fields
7. HDMI Parameters x
7.1. HDMI Source Parameters 7.2. HDMI Sink Parameters
8. HDMI Simulation Example x
8.1. Simulation Walkthrough
1. HDMI Intel® FPGA IP Quick Reference
2. HDMI Overview
3. HDMI Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI Source
6. HDMI Sink
7. HDMI Parameters
8. HDMI Simulation Example
9. HDMI Intel® FPGA IP User Guide Archives
10. Document Revision History for the HDMI Intel® FPGA IP User Guide

5.1.7. Source Auxiliary Control Port

To simplify the user logic, the source core has control ports to send the most common auxiliary control packets.

These packets are: General Control Packet, Auxiliary Video Information (AVI) InfoFrame, and HDMI Vendor Specific InfoFrame (VSI).

The core sends the default values in the auxiliary packets. The default values allow the core to send video data compatible with the HDMI 1.4b Specification with minimum description.

You can also override the generators using the customized input values. The override values replace the default values when the input checksum is non-zero.

Table 21.  Insertion and Filtration
Auxiliary Packets Insertion/Filtration Frequency of Insertion
General Control Packet (GCP) –

The core always inserts GCP packets from the GCP sideband upon the rising edge of vsync.

The core always removes the GCP in the Auxiliary Data Port.

You must provide the pixel packing and color depth information through the gcp port.

Once per frame.
Auxiliary Video Information (AVI) InfoFrame info_avi[112]=1'b0

The core inserts info_avi when there is a non-zero bit upon the rising edge of vsync.

The core send default values when all bits are zero. The core filters the AVI InfoFrame packet on the Auxiliary Data Port.

Once per frame.

Support FRL=0: info_avi[112] =1'b1

Support FRL =1: info_avi[122]=1'b1

The core does not insert info_avi.

The AVI InfoFrame packet on the Auxiliary Data Port passes through.

Vendor Specific InfoFrame (VSI) info_vsi[61]=1'b0

The core inserts info_vsi[60:0] when there is a non-zero bit upon the rising edge of vsync.

The core sends default values when all bits are zero. The core filters the VSI InfoFrame packet on the Auxiliary Data Port.

Once per frame.
info_vsi[61]=1'b1

The core does not insert info_vsi[60:0].

The VSI InfoFrame packet on the Auxiliary Data Port passes through.

Audio Metadata (AM) audio_metadata[165]=1'b0

The core inserts audio_metadata[164:0] when audio_format[3:0] is 3D audio or MST audio upon the rising edge of vsync.

The core filters the AM packet on the Auxiliary Data Port.

 Once per frame.
audio_metadata[165]=1'b1

The core does not insert audio_metadata[164:0].

The AM packet on the Auxiliary Data Port passes through.
Audio InfoFrame (AI) audio_info_ai[48]=1'b0

The core inserts audio_info_ai[47:0] when there is a non-zero bit upon the rising edge of vsync.

The core sends default values when all bits are zero. The core filters the AI packet on the Auxiliary Data Port.

Once per frame.
audio_info_ai[48]=1'b1

The core does not insert audio_info_ai[47:0].

The AI packet on the Auxiliary Data Port passes through.
Audio Control Regeneration (ACR) –

The core always inserts the audio_N and audio_CTS.

The core does not filter the ACR packet in the auxiliary. If there is ACR packet in the Auxiliary Data Port, you must remove it before passing into the Auxiliary Data Port.

Every 1 ms.
Audio Sample –

The core always inserts audio_data.

The core does not filter the audio sample packet in the Auxiliary Data Port. If there is audio sample packet in the Auxiliary Data Port, you must remove it before passing into the Auxiliary Data Port.

Based on audio sample rate.
Level Two Title