Multi Channel DMA Intel® FPGA IP for PCI Express* Release Notes

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Date 4/07/2025
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1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes
1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes x
1.1. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: v24.2.1] [P-Tile: v8.3.1] [F-Tile: v9.3.1] [R-Tile: v5.3.1]] 1.2. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: v24.2.0] [P-Tile: v8.3.0] [F-Tile: v9.3.0] [R-Tile: v5.3.0] 1.3. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: v24.2.0] [P-Tile: v8.2.0] [F-Tile: v9.2.0] [R-Tile: v5.2.0] 1.4. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: v24.1.0] [P-Tile: v8.1.0] [F-Tile: v9.1.0] [R-Tile: v5.1.0] 1.5. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v23.1.0] [P-Tile: v7.1.0] [F-Tile: v8.0.0] [R-Tile: v4.1.0] 1.6. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v23.0.0] [P-Tile: v7.0.0] [F-Tile: v7.0.0] [R-Tile: v4.0.0] 1.7. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v22.3.0] [P-Tile: v6.0.0] [F-Tile: v6.0.0] [R-Tile: v3.0.0] 1.8. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v22.2.0] [P-Tile: v5.1.0] [F-Tile: v5.1.0] [R-Tile: v2.0.0] 1.9. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v22.1.0] [P-Tile: v5.0.0] [F-Tile: v5.0.0] [R-Tile: v1.0.0] 1.10. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v22.0.0] [P-Tile: v4.0.0] [F-Tile: v4.0.0] 1.11. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v21.5.0 ] [P-Tile: v3.1.0 ] [F-Tile: v3.0.0 ] 1.12. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v21.4.0 ] [P-Tile: v3.0.0] [F-Tile: v2.0.0] 1.13. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v21.3.0] [P-Tile: v2.2.0] [F-Tile: v1.1.0] 1.14. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v21.2.0] [P-Tile: v2.1.0] [F-Tile: v1.0.0] 1.15. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v2.0.0] [H-Tile: v21.1.0] 1.16. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v1.0.0] [H-Tile: v2.0.0] 1.17. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core v20.0.0 1.18. Multi Channel DMA Intel FPGA IP for PCI Express : User Guide Archives
1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes

1.5. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v23.1.0] [P-Tile: v7.1.0] [F-Tile: v8.0.0] [R-Tile: v4.1.0]

Table 5.   [H-Tile: v23.1.0] [P-Tile: v7.1.0] [F-Tile: v8.0.0] [R-Tile: v4.1.0] : 2024.01.12
Quartus® Prime Version Description Impact
23.4

Added support for concurrent (run separately) 2x8 mode in P-Tile MCDMA IP for Stratix® 10 DX device.

You can instantiate two separate instances of P-Tile MCDMA IP Core in 2 x8 mode for Stratix® 10 DX device.

P-Tile MCDMA IP Performance values are consistent across DPDK and Custom Driver using max speed and link width

You can use DPDK or Custom Driver to get performance values.

Added support for Endpoint MSI interrupt interface in BAS and BAM+BAS modes for H-Tile MCDMA IP.

You can use MSI request interface to trigger MSI messages

Removed pld_warm_rst_rdy and link_req_rst_n interfaces from F-Tile MCDMA IP and P-Tile MCDMA IP.

These internal interfaces were exported only when "Export pld_warm_rst_rdy and link_req_rst_n interface to top level" IP parameter GUI is selected.

This IP parameter is not available on the P-Tile MCDMA IP and F-Tile MCDMA IP.

Added PTM interfaces for R-Tile MCDMA Endpoint in Ports 0 and 1.

You can use PTM interfaces to trigger PTM messages.
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