Multi Channel DMA Intel® FPGA IP for PCI Express* Release Notes

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Date 7/31/2024
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1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes
1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes x
1.1. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: 24.1.0] [P-Tile: 8.1.0] [F-Tile: 9.1.0] [R-Tile: 5.1.0] 1.2. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 23.1.0] [P-Tile: 7.1.0] [F-Tile: 8.0.0] [R-Tile: 4.1.0] 1.3. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 23.0.0] [P-Tile: 7.0.0] [F-Tile: 7.0.0] [R-Tile: 4.0.0] 1.4. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.3.0] [P-Tile: 6.0.0] [F-Tile: 6.0.0] [R-Tile: 3.0.0] 1.5. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.2.0] [P-Tile: 5.1.0] [F-Tile: 5.1.0] [R-Tile: 2.0.0] 1.6. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.1.0] [P-Tile: 5.0.0] [F-Tile: 5.0.0] [R-Tile: 1.0.0] 1.7. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.0.0] [P-Tile: 4.0.0] [F-Tile: 4.0.0] 1.8. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.5.0 ] [P-Tile: 3.1.0 ] [F-Tile: 3.0.0 ] 1.9. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.4.0 ] [P-Tile: 3.0.0] [F-Tile: 2.0.0] 1.10. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.3.0] [P-Tile: 2.2.0] [F-Tile: 1.1.0] 1.11. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.2.0] [P-Tile: 2.1.0] [F-Tile: 1.0.0] 1.12. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v2.0.0] [H-Tile: v21.1.0] 1.13. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v1.0.0] [H-Tile: v2.0.0] 1.14. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core v20.0.0 1.15. Multi Channel DMA Intel FPGA IP for PCI Express : User Guide Archives
1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes

1.13. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v1.0.0] [H-Tile: v2.0.0]

Table 13.  Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: 1.0.0] [H-Tile: 2.0.0] 2021.07.19
Quartus® Prime Version IP Version Description Impact
21.1

[P-Tile: v1.0.0]

[H-Tile: v2.0.0]

 Added support for P-Tile Gen4/Gen3 x16 (Root Port, Endpoint) and x8 (Endpoint). You can implement up to Gen4 x16 link in Stratix® 10 DX and Agilex™ 7 FPGA device families.
Added support for H-Tile Gen3 x8 and Root Port mode. You can implement Gen3 x16/x8 link in Intel Stratix 10 GX and MX device families.
Added support for various user modes: Multi channel DMA (EP), Bursting Master (RP, EP), Bursting Slave (RP, EP), BAM-BAS (RP, EP) and BAM-MCDMA (EP). You can implement a user mode that best suits your application needs based on the port usage (Root Port / Endpoint).
Added support for Configuration Slave interface for Root Port mode. You can write to/read from the downstream Endpoint configuration space registers using the Config Slave interface.
Added support for user MSI-X in MCDMA mode. You can trigger an MSI-X in MCDMA mode.
Added support for user FLR in MCDMA mode. Endpoint user logic can be reset by the Function Level Reset.
Added support for SR-IOV. You can implement multiple PFs/VFs: Up to 8 PFs in P-Tile and 4 PFs in H-Tile.
Added support for MCDMA AVST 1 port interface. AVST 1 port interface enables you to implement multiple channels of H2D/D2H DMA.
Support for increased DMA channels: -
  • AVMM Interface: up to 2K (max 512 per function)
  • AVST 1 port Interface: [P-Tile: 64] [H-Tile: 256]
You can allocate more DMA channels to a function.
Added support for D2H Descriptor Prefetch in AVST 1 port mode. You can configure the number of prefetch channels and maximum descriptor fetch.
Added support for 8-byte Metadata In MCDMA AVST mode, you can re-purpose the descriptor H2D destination address and D2H source address fields to carry application specific metadata.
Added support for DPDK PMD and Kernel mode drivers You can implement MCDMA software using these drivers.
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