Multi Channel DMA Intel® FPGA IP for PCI Express* Release Notes

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ID 683791
Date 7/31/2024
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1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes
1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes x
1.1. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: 24.1.0] [P-Tile: 8.1.0] [F-Tile: 9.1.0] [R-Tile: 5.1.0] 1.2. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 23.1.0] [P-Tile: 7.1.0] [F-Tile: 8.0.0] [R-Tile: 4.1.0] 1.3. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 23.0.0] [P-Tile: 7.0.0] [F-Tile: 7.0.0] [R-Tile: 4.0.0] 1.4. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.3.0] [P-Tile: 6.0.0] [F-Tile: 6.0.0] [R-Tile: 3.0.0] 1.5. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.2.0] [P-Tile: 5.1.0] [F-Tile: 5.1.0] [R-Tile: 2.0.0] 1.6. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.1.0] [P-Tile: 5.0.0] [F-Tile: 5.0.0] [R-Tile: 1.0.0] 1.7. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.0.0] [P-Tile: 4.0.0] [F-Tile: 4.0.0] 1.8. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.5.0 ] [P-Tile: 3.1.0 ] [F-Tile: 3.0.0 ] 1.9. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.4.0 ] [P-Tile: 3.0.0] [F-Tile: 2.0.0] 1.10. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.3.0] [P-Tile: 2.2.0] [F-Tile: 1.1.0] 1.11. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.2.0] [P-Tile: 2.1.0] [F-Tile: 1.0.0] 1.12. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v2.0.0] [H-Tile: v21.1.0] 1.13. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v1.0.0] [H-Tile: v2.0.0] 1.14. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core v20.0.0 1.15. Multi Channel DMA Intel FPGA IP for PCI Express : User Guide Archives
1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes

1.6. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.1.0] [P-Tile: 5.0.0] [F-Tile: 5.0.0] [R-Tile: 1.0.0]

Table 6.  Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.1.0] [P-Tile: 5.0.0] [F-Tile: 5.0.0] [R-Tile: 1.0.0] : 2022.12.27
Quartus® Prime Version IP Version Description Impact
22.4

[H-Tile: 22.1.0]

[P-Tile: 5.0.0]

[F-Tile: 5.0.0]

[R-Tile: 1.0.0]

The default User Mode parameter on m1 instance fixed when Root Port Mode is selected.

Users can implement MCDMA IP in Root Port Mode.

Fixed the MCDMA P-Tile BAM performance issue when BAM+BAS Mode and Traffic Generator/Checker Design Example is compiled.

Hardware is capable to reach expected performance.

Initial release of MCDMA R-Tile IP Core. Added support for R-Tile Gen5 x8, Gen4/Gen3 x16 and Gen4/Gen3 x8 (Root Port,Endpoint).

MCDMA R-Tile Hardware support is available in Quartus® Prime 22.4 Release Patch 0.02.

Users can implement up to Gen5 x8 link in the Agilex™ 7 FPGA devices using R-Tile.

Added support for BAM-BAS-MCDMA (EP) user mode, for MCDMA H-Tile, P-Tile and F-Tile IP Cores.

Users can now use BAM, BAS and MCDMA modes simultaneously in Endpoint mode applications.

R-Tile MCDMA Design Example simulations are not supported in this Quartus® Prime release.

-

MCDMA R-Tile MSI, simultaneous BAM+BAS+MCDMA and Root Port ATT features in the Quartus® Prime GUI are not supported

Support for these features may be added in a future Quartus® Prime release.

Removed pld_clrpcs_n_i input from MCDMA P-Tile IP Core. New reset signals (p#_warm_perst_n_i, p#_cold_perst_n_i) are exported to the top-level block symbol when independent resets are enabled.

IP Upgrade tool does not upgrade automatically and requires manual upgrade (Upgrade in Editor).

If pld_clrpcs_n_i reset was used by application logic, switch to new reset signals input before manual upgrade.

Removed support for kernel mode Char driver.

Users can use netdev (kernel mode) driver and custom and DPDK (user mode) driver.

Added support for Independent cold and warm reset operations for the ports in the x8x8 Endpoint in F-Tile.

New reset signals (i_gpio_perst#_n) are exported to the top-level block symbol when independent resets are enabled.

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