Multi Channel DMA Intel® FPGA IP for PCI Express* Release Notes

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ID 683791
Date 11/04/2024
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1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes
1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes x
1.1. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: 24.2.0] [P-Tile: 8.2.0] [F-Tile: 9.2.0] [R-Tile: 5.2.0] 1.2. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: 24.1.0] [P-Tile: 8.1.0] [F-Tile: 9.1.0] [R-Tile: 5.1.0] 1.3. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 23.1.0] [P-Tile: 7.1.0] [F-Tile: 8.0.0] [R-Tile: 4.1.0] 1.4. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 23.0.0] [P-Tile: 7.0.0] [F-Tile: 7.0.0] [R-Tile: 4.0.0] 1.5. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.3.0] [P-Tile: 6.0.0] [F-Tile: 6.0.0] [R-Tile: 3.0.0] 1.6. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.2.0] [P-Tile: 5.1.0] [F-Tile: 5.1.0] [R-Tile: 2.0.0] 1.7. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.1.0] [P-Tile: 5.0.0] [F-Tile: 5.0.0] [R-Tile: 1.0.0] 1.8. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.0.0] [P-Tile: 4.0.0] [F-Tile: 4.0.0] 1.9. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.5.0 ] [P-Tile: 3.1.0 ] [F-Tile: 3.0.0 ] 1.10. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.4.0 ] [P-Tile: 3.0.0] [F-Tile: 2.0.0] 1.11. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.3.0] [P-Tile: 2.2.0] [F-Tile: 1.1.0] 1.12. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.2.0] [P-Tile: 2.1.0] [F-Tile: 1.0.0] 1.13. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v2.0.0] [H-Tile: v21.1.0] 1.14. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v1.0.0] [H-Tile: v2.0.0] 1.15. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core v20.0.0 1.16. Multi Channel DMA Intel FPGA IP for PCI Express : User Guide Archives
1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes

1.5. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.3.0] [P-Tile: 6.0.0] [F-Tile: 6.0.0] [R-Tile: 3.0.0]

Table 5.  Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.3.0] [P-Tile: 6.0.0] [F-Tile: 6.0.0] [R-Tile: 3.0.0] : 2023.06.26
Quartus® Prime Version IP Version Description Impact
23.2

[H-Tile: 22.3.0]

[P-Tile: 6.0.0]

[F-Tile: 6.0.0]

[R-Tile: 3.0.0]

Added support for 4x4 bifurcation mode only Root Port in P-Tile MCDMA IP.

P-Tile MCDMA IP Design Example Root Port simulation and hardware are not supported.

You can instantiate 4x4 separate instances of P-Tile MCDMA IP Core in x4 mode in Root Port only.

Added support for independent and concurrent Gen4/3 4x4 bifurcation mode in R-Tile MCDMA IP.

R-Tile MCDMA IP Design Example Root Port simulation and hardware are not supported.

R-Tile MCDMA IP Design Example Endpoint simulation is not supported.
You can instantiate 4 separate instances of R-Tile MCDMA IP Core in x4 mode in Root Port and Endpoint:
  • Endpoint / Endpoint / Endpoint / Endpoint
  • Endpoint / Endpoint / Root port / Root port
  • Endpoint / Root port / Root port / Root port
  • Root port / Root port / Root port / Root port

R-Tile MCDMA IP in 4x4 Port 2 and 3 don't support SRIOV, FLR, MSI-X and MSI features. These ports only support BAM, BAS and BAM+BAS User Modes

R-Tile MCDMA Endpoint has limited support for port 2 and 3.
Added new Hard IP Mode options and PLD clock frequencies support below for F-Tile MCDMA IP:
  • Gen4 1x4, Interface - 128 bit (PLD Clock Frequency 500 MHz / 450 MHz / 400 MHz / 350 MHz) for endpoint
  • Gen3 1x4, Interface - 128 bit (PLD Clock Frequency 250 MHz) for endpoint
  • Gen4 2x4, Interface - 128 bit (PLD Clock Frequency 500 MHz / 450 MHz / 400 MHz / 350 MHz) for root port
  • Gen3 2x4, Interface - 128 bit (PLD Clock Frequency 250 MHz) for root port
  • Gen4 4x4, Interface - 128 bit (PLD Clock Frequency 500 MHz / 450 MHz / 400 MHz / 350 MHz) for root port
  • Gen3 4x4, Interface - 128 bit (PLD Clock Frequency 250 MHz) for root port

You can generate the IP with the newly supported Hard IP Mode but not the design example.

Fixed vector masking capability for User Event MSI-X interrupt in MCDMA IP.

MCDMA IP is capable to mask User Event MSI-X interrupt when mask-bit is set in the vector control register.
Added the following new Hard IP Modes and PLD clock frequencies support for P-Tile MCDMA IP:
  • Gen4 4x4 Interface - 128 bit (PLD Clock Frequency 500 MHz / 450 MHz / 400 MHz / 350 MHz)
  • Gen3 4x4 Interface - 128 bit (PLD Clock Frequency 250 MHz)

PCIe port bifurcation x4 is now supported by P-Tile MCDMA IP.

Added support for Root Port Address Translation Table in BAS and BAM+BAS modes (R-Tile MCDMA IP)

You can use ATT to access the 64-bit PCIe address space.
Added the following new Hard IP Modes and PLD clock frequencies support for R-Tile MCDMA IP:
  • Gen4/Gen3 4x4 Interface - 256 bits (PLD Clock Frequency 300 MHz / 275 MHz / 250 MHz)
  • Gen4 4x4 Interface - 128 bits (PLD Clock Frequency 500 MHz / 475 MHz / 450 MHz / 425 MHz / 400 MHz)
  • Gen3 4x4 Interface - 128 bits (PLD Clock Frequency 300 MHz / 275 MHz / 250 MHz)

PCIe port bifurcation is now supported by R-Tile MCDMA IP.

Added support for Endpoint MSI interrupt request interface in BAS and BAM+BAS modes (R-Tile MCDMA IP)

You can use MSI request interface to trigger MSI messages.

Added support for concurrent 2x8 bifurcation mode in R-Tile MCDMA IP

You can instantiate two separate instances of R-Tile MCDMA IP Core in x8 mode.

Fixed dropping Posted Writes in P-Tile MCDMA AVMM PIO when user logic backpressures by asserting rx_pio_waitrequest_i

MCDMA AVMM interface handles PIO wait request from user logic when there are Posted Writes back-to-back into the AVMM PIO.
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