Multi Channel DMA Intel® FPGA IP for PCI Express* Release Notes

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ID 683791
Date 7/31/2024
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1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes
1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes x
1.1. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: 24.1.0] [P-Tile: 8.1.0] [F-Tile: 9.1.0] [R-Tile: 5.1.0] 1.2. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 23.1.0] [P-Tile: 7.1.0] [F-Tile: 8.0.0] [R-Tile: 4.1.0] 1.3. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 23.0.0] [P-Tile: 7.0.0] [F-Tile: 7.0.0] [R-Tile: 4.0.0] 1.4. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.3.0] [P-Tile: 6.0.0] [F-Tile: 6.0.0] [R-Tile: 3.0.0] 1.5. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.2.0] [P-Tile: 5.1.0] [F-Tile: 5.1.0] [R-Tile: 2.0.0] 1.6. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.1.0] [P-Tile: 5.0.0] [F-Tile: 5.0.0] [R-Tile: 1.0.0] 1.7. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.0.0] [P-Tile: 4.0.0] [F-Tile: 4.0.0] 1.8. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.5.0 ] [P-Tile: 3.1.0 ] [F-Tile: 3.0.0 ] 1.9. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.4.0 ] [P-Tile: 3.0.0] [F-Tile: 2.0.0] 1.10. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.3.0] [P-Tile: 2.2.0] [F-Tile: 1.1.0] 1.11. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.2.0] [P-Tile: 2.1.0] [F-Tile: 1.0.0] 1.12. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v2.0.0] [H-Tile: v21.1.0] 1.13. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v1.0.0] [H-Tile: v2.0.0] 1.14. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core v20.0.0 1.15. Multi Channel DMA Intel FPGA IP for PCI Express : User Guide Archives
1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes

1.3. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 23.0.0] [P-Tile: 7.0.0] [F-Tile: 7.0.0] [R-Tile: 4.0.0]

Table 3.  Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 23.0.0] [P-Tile: 7.0.0] [F-Tile: 7.0.0] [R-Tile: 4.0.0] : 2023.10.03
Quartus® Prime Version IP Version Description Impact
23.3

[H-Tile: 23.0.0]

[P-Tile: 7.0.0]

[F-Tile: 7.0.0]

[R-Tile: 4.0.0]

Fixed stability netdev_app tool issues on Network Device Driver with PIO bypass mode test.

netdev_app won't see instability issues on PIO bypass mode test.

R-Tile MCDMA IP added support for Configuration via Protocol (CVP) flow for a single tile only.

You can configure the FPGA using CVP flows.

Added support for PIPE Mode Simulation for R-Tile MCDMA IP only.

When enabled, the R-Tile MCDMA IP exposes PIPE interface.

This interface is used to connect a BFM with PIPE interface support and improve the overall simulation time.

Added Design Example simulation support for R-Tile PIO with MCDMA Bypass Mode in Xcelium* , QuestaSim* and Questa* Intel® FPGA Edition.

You can only simulate PIO using MCDMA Bypass Mode with all supported User Modes up to Gen5 x8 link in the Agilex™ 7 I-Series FPGA devices using R-Tile.

Added a new Hard IP Modes and PLD clock frequencies support for R-Tile MCDMA IP:
  • Gen5 4x4 Interface - 256 bits (PLD Clock Frequency 500 MHz / 475 MHz / 450 MHz / 425 MHz / 400 MHz)

You can implement Gen5 4x4 link in the Agilex™ 7 FPGA devices using R-Tile MCDMA IP.

Removed pld_warm_rst_rdy and link_req_rst_n interfaces from R-Tile MCDMA IP.

These internal interfaces were exported only when Export pld_warm_rst_rdy and link_req_rst_n interface to top level parameter selected.

This IP parameter is not available on the R-Tile MCDMA IP.

Software directory is created multiple times depending on the number of Hard IP ports selected. pX_software folder where X = 0, 1, 2, 3.

Software folder is specific to the example design and IP port.

You must use the corresponding software folder with each IP port.

Added support to request memory PIO read and write with custom driver.

You can read and write from PIO address range in bar 2 from any valid custom memory.

Fixed MCDMA Custom Driver issue for Ubuntu 22.04 LTS operating system when Virtual Function I/O (VFIO) kernel mode and MSIX mode are set.

You can use it with VFIO kernel and MSIX mode.

Added Analog Parameters tab in the IP Parameter Editor for F-Tile MCDMA IP to enable transceiver analog settings for low loss PCIe design.

You should only enable this parameter for chip to chip PCIe design with F-Tile to ensure good link quality.
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