Multi Channel DMA Intel® FPGA IP for PCI Express* Release Notes

Download PDF
ID 683791
Date 7/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes
1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes x
1.1. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: 24.1.0] [P-Tile: 8.1.0] [F-Tile: 9.1.0] [R-Tile: 5.1.0] 1.2. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 23.1.0] [P-Tile: 7.1.0] [F-Tile: 8.0.0] [R-Tile: 4.1.0] 1.3. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 23.0.0] [P-Tile: 7.0.0] [F-Tile: 7.0.0] [R-Tile: 4.0.0] 1.4. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.3.0] [P-Tile: 6.0.0] [F-Tile: 6.0.0] [R-Tile: 3.0.0] 1.5. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.2.0] [P-Tile: 5.1.0] [F-Tile: 5.1.0] [R-Tile: 2.0.0] 1.6. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.1.0] [P-Tile: 5.0.0] [F-Tile: 5.0.0] [R-Tile: 1.0.0] 1.7. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.0.0] [P-Tile: 4.0.0] [F-Tile: 4.0.0] 1.8. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.5.0 ] [P-Tile: 3.1.0 ] [F-Tile: 3.0.0 ] 1.9. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.4.0 ] [P-Tile: 3.0.0] [F-Tile: 2.0.0] 1.10. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.3.0] [P-Tile: 2.2.0] [F-Tile: 1.1.0] 1.11. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.2.0] [P-Tile: 2.1.0] [F-Tile: 1.0.0] 1.12. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v2.0.0] [H-Tile: v21.1.0] 1.13. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v1.0.0] [H-Tile: v2.0.0] 1.14. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core v20.0.0 1.15. Multi Channel DMA Intel FPGA IP for PCI Express : User Guide Archives
1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes

1.11. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.2.0] [P-Tile: 2.1.0] [F-Tile: 1.0.0]

Table 11.  Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.2.0] [P-Tile: 2.1.0] [F-Tile: 1.0.0] : 2021.11.24
Quartus® Prime Version IP Version Description Impact
21.3

[H-Tile: 21.2.0]

[P-Tile: 2.1.0]

[F-Tile: 1.0.0]

 Added Intel Stratix 10 DX P-Tile Production FPGA Development Kit option for Target Development Kit Allow users to generate design example with Intel Stratix 10 DX P-Tile Production FPGA Development Kit board settings.
Removed coreclkout_hip output from MCDMA P-Tile IP Core IP Upgrade tool doesn't upgrade automatically and requires manual upgrade (Upgrade in Editor). If this clock was used by application logic, switch to app_clk output before manual upgrade.
Reduced Root Port Config Slave interface address (cs_address_i) width from 29 bits to 14 bits This allows users to save system memory space. Requires 2 clock cycles to perform config read/write to Endpoint configuration registers.
Increased DMA channel support to 2K for MCDMA AVST 1 port mode Enables DMA bandwidth sharing up to 2K channels. This enables more VMs/PFs/VFs to utilize MCDMA to perform data move between the Host and device.
Added support for "Traffic generator/checker" example design for BAS in EP mode and corresponding s/w support.

User can test the example application for BAS transactions.

User needs to select ''BAM_BAS" user mode in the IP.
Added MCDMA IP NetDev Mode driver

MCDMA network driver exposes the device as ethernet device.

All TCP/IP socket based applications can use this driver to perform data transfer by using DMA.

User needs to select "Device-side packet loopback" example design.

Initial release of MCDMA F-Tile IP Core. Added support for F-Tile Gen4/Gen3 x16 (Root Port,Endpoint) and x8 (Endpoint).

You can implement up to Gen4 x16 link in the Intel Stratix 10 and Intel Agilex FPGA devices using F-Tile.
Support for AVST 1 port 2K DMA channels Enables DMA bandwidth sharing up to 2K channels.
BAS Support IP, Example design, Software enhanced to support BAS.
Added Support for kernel net-dev driver. MCDMA network driver, exposes the device as ethernet device. All TCP/IP socket based applications, can use this driver to perform data transfer by using DMA.
Initial release of Debug Toolkit for MCDMA P-Tile IP Core You can use the Debug Toolkit to monitor link status and various config registers for diagnostic and debugging purpose.
Level Two Title