AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

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ID 683776
Date 12/30/2015
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Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow) x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Reference Design Files 1.5. FPGA Pin Assignments 1.6. System Parameters 1.7. Reference Design Software 1.8. Customizing the Reference Design 1.9. AN 755 Document Revision History
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Hardware Setup 1.2.3. Compiling the HDL and Programming the Board 1.2.4. Setting up the Software Command Line Environment
1.3. Reference Design Components x
1.3.1. Qsys System 1.3.2. Core PLL 1.3.3. Transport Layer 1.3.4. Test Pattern Generator 1.3.5. Test Pattern Checker
1.3.1. Qsys System x
1.3.1.1. Top Level Qsys Address Map 1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals 1.3.1.3. JESD204B Subsystem
1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals x
1.3.1.2.1. ARM HPS Control Unit 1.3.1.2.2. FPGA Core Control and Status PIO 1.3.1.2.3. SPI Master Module
1.3.1.3. JESD204B Subsystem x
1.3.1.3.1. JESD204B IP Core 1.3.1.3.2. Reset Sequencer 1.3.1.3.3. Transceiver PHY Reset Controller 1.3.1.3.4. Avalon-MM Bridge 1.3.1.3.5. JESD204B Subsystem Address Map
1.7. Reference Design Software x
1.7.1. User Commands 1.7.2. Dynamic Reconfiguration 1.7.3. Software Interrupt Service Routines (ISR) 1.7.4. Software Parameters 1.7.5. Software Functions Description
1.7.5. Software Functions Description x
1.7.5.1. Functions in main.c Source File 1.7.5.2. Functions in rules.c Source File 1.7.5.3. Custom Peripheral Access Macros in macros.c Source File
1.8. Customizing the Reference Design x
1.8.1. Modifying JESD204B IP Core Parameters 1.8.2. Modifying the Data Rate or Reference Clock Frequency 1.8.3. Implementing a Multi-Link Design
1.8.3. Implementing a Multi-Link Design x
1.8.3.1. Editing the Qsys Project 1.8.3.2. Editing the Top Level HDL File 1.8.3.3. Editing the Software Source Code
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

1.7.4. Software Parameters

Various behaviors of the main.c source code are controlled by software parameters defined in the main header file, main.h.

Table 16.  Software ParametersThis table lists the software parameters and description.

Parameter

Description

Default Value

DEBUG_MODE

Set to 1 to print debug messages, else set to 0.

0

PRINT_INTERRUPT_ MESSAGES

Set to 1 to print JESD204B error interrupt messages, else set to 0.

1

CONFIG_SPI

Set to 1 to configure external converters via SPI interface at start of main.c execution, else set to 0.

1

PATCHK_EN

Set to 1 when test pattern checker is included in the initial design configuration, else set to 0.

1

ALTERA_TRANSPORT_ LAYER

Set to 1 when using Altera transport layer, else set to 0.

1

BONDED

Set to 1 when transceivers configured in bonded mode, set to 0 when transceivers configured in unbonded mode.

0

DATAPATH

Set to indicate JESD204B IP configuration:

  • 1: TX data path only
  • 2: RX data path only
  • 3: Duplex data path (TX and RX data path)

3

DATA_RATE_LINK_n

Set to indicate the initially configured serial data rate of link n in Mbps (for example, to set link 0 to 6144 Mbps, DATA_RATE_LINK_ 0=6144). For multi-link scenarios, add additional DATA_RATE_ LINK_n parameters to the DR_init[] array in main.c.

Note: Data rate reconfiguration is not supported in this reference design.

6144

DATA_RATE_MIN

Set to indicate the minimum serial data rate (in Mbps) supported by the JESD204B IP core for the following device families:

  • Arria V GZ, Arria 10, Stratix V: 2000
  • Arria V: 1000
Note: Data rate reconfiguration is not supported in this reference design.

2000

MAX_LINKS

Set to indicate the number of links in the design (for example, for dual link, set MAX_LINKS=2)

Note: When using the design as-is, the maximum value of MAX_ LINKS is 4. To increase the limit, redesign the address map in QSYS.

1

LINE_BUFFER

Sets the maximum number of characters that user can enter on command line.

100

MAX_NUM_OPTIONS

Sets the maximum number of options per command.

20

MAX_OPTIONS_CHAR

Sets the maximum number of characters per command option

10

LOOPBACK_INIT

Initial value of loopback. Set to 1 for internal serial loopback mode, else set to 0.

1

SOURCEDEST_INIT

Initial value of source/destination. Set to indicate test pattern generator/checker type or user mode:

  • USER: User mode (no test pattern generator/checker in data path).
  • ALT: Test pattern generator/checker set in alternate checkerboard mode.
  • RAMP: Test pattern generator/checker set in ramp wave mode.
  • PRBS: Test pattern generator/checker set in parallel PRBS mode.

PRBS

F1_FRAMECLK_DIV

Set to the F1_FRAMECLK_DIV parameter as defined in the top level HDL file (jesd204b_ed.sv).

4

F2_FRAMECLK_DIV

Set to the F2_FRAMECLK_DIV parameter as defined in the top level HDL file (jesd204b_ed.sv).

2

SOC

Set to 1 if source code is targeting ARM® HPS. Set to 0 if source code is targeting soft Nios II processor.

1

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